From 0296c808691d0ccb68f05209c44504e0119ab703 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 8 May 2022 13:00:43 +0100 Subject: [PATCH] add code-comments explaining that setvl, svstep svremap and svshape are all 32-bit *only* as they are *control* instructions not themselves vector instructions --- src/openpower/sv/trans/svp64.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index b1954160..62baf5ec 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -186,6 +186,11 @@ class SVP64Asm: fields.append(macro_subst(macros, field)) log("opcode, fields substed", ls, opcode, fields) + # this is a *32-bit-only* instruction. it controls SVSTATE. + # it is *not* a 64-bit-prefixed Vector instruction (no sv.setvl), + # it is a Vector *control* instruction. + # note: EXT022 is the "sandbox" major opcode so it's fine to add + # sigh have to do setvl here manually for now... # note the subtract one from SVi. if opcode in ["setvl", "setvl."]: @@ -204,6 +209,11 @@ class SVP64Asm: yield ".long 0x%x" % insn return + # this is a *32-bit-only* instruction. it updates SVSTATE. + # it is *not* a 64-bit-prefixed Vector instruction (no sv.svstep), + # it is a Vector *control* instruction. + # note: EXT022 is the "sandbox" major opcode so it's fine to add + # sigh have to do setvl here manually for now... # note the subtract one from SVi. if opcode in ["svstep", "svstep."]: @@ -219,6 +229,11 @@ class SVP64Asm: yield ".long 0x%x" % insn return + # this is a *32-bit-only* instruction. it updates SVSHAPE and SVSTATE. + # it is *not* a 64-bit-prefixed Vector instruction (no sv.svshape), + # it is a Vector *control* instruction. + # note: EXT022 is the "sandbox" major opcode so it's fine to add + # and svshape. note that the dimension fields one subtracted from each if opcode == 'svshape': insn = 22 << (31-5) # opcode 22, bits 0-5 @@ -234,6 +249,11 @@ class SVP64Asm: yield ".long 0x%x" % insn return + # this is a *32-bit-only* instruction. it updates the SVSHAPE SPR + # it is *not* a 64-bit-prefixed Vector instruction (no sv.svremap), + # it is a Vector *control* instruction. + # note: EXT022 is the "sandbox" major opcode so it's fine to add + # and svremap if opcode == 'svremap': insn = 22 << (31-5) # opcode 22, bits 0-5 @@ -251,6 +271,12 @@ class SVP64Asm: yield ".long 0x%x" % insn return + # ok from here-on down these are added as 32-bit instructions + # and are here only because binutils (at present) doesn't have + # them (that's being fixed!) + # they can - if implementations then choose - be Vectorised + # (sv.fsins) because they are general-purpose scalar instructions + # and fsins # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG # however we are out of space with opcode 22 -- 2.30.2