From 02a03501e439cd92b741034c32ce7238a927dff1 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Thu, 11 Jan 2018 22:32:41 +0000 Subject: [PATCH] rs6000-builtin.def (BU_P7_MISC_X): New #define. [gcc] 2018-01-11 Bill Schmidt * config/rs6000/rs6000-builtin.def (BU_P7_MISC_X): New #define. (SPEC_BARRIER): New instantiation of BU_P7_MISC_X. * config/rs6000/rs6000.c (rs6000_expand_builtin): Handle MISC_BUILTIN_SPEC_BARRIER. (rs6000_init_builtins): Likewise. * config/rs6000/rs6000.md (UNSPECV_SPEC_BARRIER): New UNSPECV enum value. (speculation_barrier): New define_insn. * doc/extend.texi: Document __builtin_speculation_barrier. [gcc/testsuite] 2018-01-11 Bill Schmidt * gcc.target/powerpc/spec-barr-1.c: New file. From-SVN: r256557 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/rs6000/rs6000-builtin.def | 13 +++++++++++++ gcc/config/rs6000/rs6000.c | 8 ++++++++ gcc/config/rs6000/rs6000.md | 6 ++++++ gcc/doc/extend.texi | 1 + gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/powerpc/spec-barr-1.c | 10 ++++++++++ 7 files changed, 54 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/spec-barr-1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3a37576a7a9..70abf60ce84 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2018-01-11 Bill Schmidt + + * config/rs6000/rs6000-builtin.def (BU_P7_MISC_X): New #define. + (SPEC_BARRIER): New instantiation of BU_P7_MISC_X. + * config/rs6000/rs6000.c (rs6000_expand_builtin): Handle + MISC_BUILTIN_SPEC_BARRIER. + (rs6000_init_builtins): Likewise. + * config/rs6000/rs6000.md (UNSPECV_SPEC_BARRIER): New UNSPECV + enum value. + (speculation_barrier): New define_insn. + * doc/extend.texi: Document __builtin_speculation_barrier. + 2018-01-11 Jakub Jelinek PR target/83203 diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 06c0c114fee..4fc130138cd 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -638,6 +638,14 @@ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ +#define BU_P7_MISC_X(ENUM, NAME, ATTR) \ + RS6000_BUILTIN_X (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_POPCNTD, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_nothing) /* ICODE */ + /* Miscellaneous builtins for instructions added in ISA 2.07. These instructions do require the ISA 2.07 vector support, but they aren't vector @@ -2324,6 +2332,11 @@ BU_DFP_MISC_2 (DSCLIQ, "dscliq", CONST, dfp_dscli_td) BU_DFP_MISC_2 (DSCRI, "dscri", CONST, dfp_dscri_dd) BU_DFP_MISC_2 (DSCRIQ, "dscriq", CONST, dfp_dscri_td) +/* 0 argument void function that we pretend was added in ISA 2.06. + It's a special nop recognized by 2018+ firmware for P7 and up, + with speculation barrier semantics. */ +BU_P7_MISC_X (SPEC_BARRIER, "rs6000_speculation_barrier", MISC) + /* 1 argument BCD functions added in ISA 2.06. */ BU_P7_MISC_1 (CDTBCD, "cdtbcd", CONST, cdtbcd) BU_P7_MISC_1 (CBCDTD, "cbcdtd", CONST, cbcdtd) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 0a0b49422d8..840b83c6e10 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16792,6 +16792,12 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case RS6000_BUILTIN_CPU_SUPPORTS: return cpu_expand_builtin (fcode, exp, target); + case MISC_BUILTIN_SPEC_BARRIER: + { + emit_insn (gen_rs6000_speculation_barrier ()); + return NULL_RTX; + } + case ALTIVEC_BUILTIN_MASK_FOR_LOAD: case ALTIVEC_BUILTIN_MASK_FOR_STORE: { @@ -17164,6 +17170,8 @@ rs6000_init_builtins (void) ftype = build_function_type_list (void_type_node, NULL_TREE); def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT); + def_builtin ("__builtin_rs6000_speculation_barrier", ftype, + MISC_BUILTIN_SPEC_BARRIER); ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node, NULL_TREE); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b718e209e3a..6b9de4262b6 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -168,6 +168,7 @@ UNSPECV_MFFS ; Move from FPSCR UNSPECV_MTFSF ; Move to FPSCR Fields UNSPECV_SPLIT_STACK_RETURN ; A camouflaged return + UNSPECV_SPEC_BARRIER ; Speculation barrier ]) @@ -12996,6 +12997,11 @@ return "ori 1,1,0"; return "ori 2,2,0"; }) + +(define_insn "rs6000_speculation_barrier" + [(unspec_volatile:BLK [(const_int 0)] UNSPECV_SPEC_BARRIER)] + "" + "ori 31,31,0") ;; Define the subtract-one-and-jump insns, starting with the template ;; so loop.c knows what to generate. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 84640f4fde6..f3e4a63ab46 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -15753,6 +15753,7 @@ unsigned long __builtin_divdeuo (unsigned long, unsigned long); unsigned int cdtbcd (unsigned int); unsigned int cbcdtd (unsigned int); unsigned int addg6s (unsigned int, unsigned int); +void __builtin_rs6000_speculation_barrier (void); @end smallexample The @code{__builtin_divde}, @code{__builtin_divdeo}, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 31ed14c16bd..cdd0ae2d42c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-01-11 Bill Schmidt + + * gcc.target/powerpc/spec-barr-1.c: New file. + 2018-01-11 H.J. Lu PR target/83330 diff --git a/gcc/testsuite/gcc.target/powerpc/spec-barr-1.c b/gcc/testsuite/gcc.target/powerpc/spec-barr-1.c new file mode 100644 index 00000000000..94293ab3706 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/spec-barr-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-mcpu=power7" } */ + +void foo () +{ + __builtin_rs6000_speculation_barrier (); +} + +/* { dg-final { scan-assembler "ori 31,31,0" } } */ -- 2.30.2