From 02c951d3e20b9ff4ad985f692dd4c0e29f9a2c89 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 26 Jun 2019 04:37:12 +0100 Subject: [PATCH] add potential MV.X and swizzle-mv --- .../specification/discussion.mdwn | 46 +++++++++++++++++++ simple_v_extension/sv_prefix_proposal.rst | 14 +++--- 2 files changed, 53 insertions(+), 7 deletions(-) diff --git a/simple_v_extension/specification/discussion.mdwn b/simple_v_extension/specification/discussion.mdwn index b04129982..424231fa4 100644 --- a/simple_v_extension/specification/discussion.mdwn +++ b/simple_v_extension/specification/discussion.mdwn @@ -80,3 +80,49 @@ TODO: adapt to the above rules. 28: add a2, a2, t1 # increment pointer to y by vl*8 2c: bnez a0, loop # repeat if n != 0 30: ret # return + +---- + +swizzle needs a MV. see below for a potential way to use the funct7 to do a swizzle in rs2. + ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| Encoding | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:2 | 1:0 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| RV32-I-type + imm[11:0] + rs1[4:0] + funct3 | rd[4:0] + opcode + 0b11 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| RV32-I-type + rsv[11:8] swizzle[7:0] + rs1[4:0] + 0b000 | rd[4:0] + OP-V + 0b11 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ + +* funct3 = MV +* OP-V = 0b1010111 + +swizzle (only active on SV or P48/P64 when SUBVL!=0): + ++-----+---+ +| 1:0 | x | ++-----+---+ +| 3:2 | y | ++-----+---+ +| 5:4 | z | ++-----+---+ +| 7:6 | w | ++-----+---+ + +---- + +potential MV.X? register-version of MV-swizzle? + ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| Encoding | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:2 | 1:0 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| RV32-R-type + funct7 + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0] + opcode + 0b11 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| RV32-R-type + 0b0000000 + rs2[4:0] + rs1[4:0] + 0b001 | rd[4:0] + OP-V + 0b11 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ + +* funct3 = MV.X +* OP-V = 0b1010111 +* funct7 = 0b0000000 + +potential funct7 = 0b0000001 to say that rs2 is a swizzle argument? + diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst index ef0ac9a43..08d554108 100644 --- a/simple_v_extension/sv_prefix_proposal.rst +++ b/simple_v_extension/sv_prefix_proposal.rst @@ -208,19 +208,19 @@ this is now set to "0b0111111". +--------------+-------+--------+--------+--------+--------+ | Encoding | 63 | 62 | 61 | 60 | 59:48 | +--------------+-------+--------+--------+--------+--------+ -| P64-LD-type | rd[6] | rs1[6] | | | VLtyp | +| P64-LD-type | rd[6] | rs1[6] | | *Rsvd* | VLtyp | +--------------+-------+--------+--------+--------+--------+ -| P64-ST-type | | rs1[6] | rs2[6] | | VLtyp | +| P64-ST-type | | rs1[6] | rs2[6] | *Rsvd* | VLtyp | +--------------+-------+--------+--------+--------+--------+ -| P64-R-type | rd[6] | rs1[6] | rs2[6] | | VLtyp | +| P64-R-type | rd[6] | rs1[6] | rs2[6] | *Rsvd* | VLtyp | +--------------+-------+--------+--------+--------+--------+ -| P64-I-type | rd[6] | rs1[6] | | | VLtyp | +| P64-I-type | rd[6] | rs1[6] | | *Rsvd* | VLtyp | +--------------+-------+--------+--------+--------+--------+ -| P64-U-type | rd[6] | | | | VLtyp | +| P64-U-type | rd[6] | | | *Rsvd* | VLtyp | +--------------+-------+--------+--------+--------+--------+ -| P64-FR-type | | rs1[6] | rs2[6] | | VLtyp | +| P64-FR-type | | rs1[6] | rs2[6] | *Rsvd* | VLtyp | +--------------+-------+--------+--------+--------+--------+ -| P64-FI-type | rd[6] | rs1[6] | rs2[6] | | VLtyp | +| P64-FI-type | rd[6] | rs1[6] | rs2[6] | *Rsvd* | VLtyp | +--------------+-------+--------+--------+--------+--------+ | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp | +--------------+-------+--------+--------+--------+--------+ -- 2.30.2