From 02d9e7000168c563a77696d760fc7547cfc9db4a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 9 May 2020 00:01:22 +0100 Subject: [PATCH] add comments --- src/soc/alu/input_stage.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py index a692a57a..021ac8ab 100644 --- a/src/soc/alu/input_stage.py +++ b/src/soc/alu/input_stage.py @@ -14,7 +14,7 @@ class ALUInputStage(PipeModBase): super().__init__(pspec, "input") def ispec(self): - return ALUInputData(self.pspec) + return ALUInputData(self.pspec) # XXX TODO, change to ALUFirstInputData def ospec(self): return ALUInputData(self.pspec) @@ -33,6 +33,8 @@ class ALUInputStage(PipeModBase): comb += self.o.a.eq(a) + # TODO: remove this because it's handled by the Computational Unit? + # If there's an immediate, set the B operand to that with m.If(self.i.ctx.op.imm_data.imm_ok): comb += self.o.b.eq(self.i.ctx.op.imm_data.imm) -- 2.30.2