From 02dac874dd57c9b985dedc3a593d74bde154d15f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 6 May 2021 17:17:19 +0100 Subject: [PATCH] improve format of docstrings for ISACaller SVP64 tests --- .../decoder/isa/test_caller_svp64.py | 50 +++++++++++++------ 1 file changed, 36 insertions(+), 14 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64.py b/src/openpower/decoder/isa/test_caller_svp64.py index 05bc22bb..3e240de1 100644 --- a/src/openpower/decoder/isa/test_caller_svp64.py +++ b/src/openpower/decoder/isa/test_caller_svp64.py @@ -22,6 +22,13 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) def test_sv_load_store(self): + """>>> lst = ["addi 1, 0, 0x0010", + "addi 2, 0, 0x0008", + "addi 5, 0, 0x1234", + "addi 6, 0, 0x1235", + "sv.stw 5.v, 0(1.v)", + "sv.lwz 9.v, 0(1.v)"] + """ lst = SVP64Asm(["addi 1, 0, 0x0010", "addi 2, 0, 0x0008", "addi 5, 0, 0x1234", @@ -43,9 +50,12 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64)) def test_sv_add(self): - # adds: - # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 - # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 + """>>> lst = ['sv.add 1.v, 5.v, 9.v' + ] + adds: + * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 + * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 + """ isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v' ]) lst = list(isa) @@ -72,9 +82,11 @@ class DecoderTestCase(FHDLTestCase): self._check_regs(sim, expected_regs) def test_sv_add_2(self): - # adds: - # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 - # r1 is scalar so ENDS EARLY + """>>> lst = ['sv.add 1, 5.v, 9.v' ] + adds: + * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 + * r1 is scalar so ENDS EARLY + """ isa = SVP64Asm(['sv.add 1, 5.v, 9.v' ]) lst = list(isa) @@ -100,9 +112,12 @@ class DecoderTestCase(FHDLTestCase): self._check_regs(sim, expected_regs) def test_sv_add_3(self): - # adds: - # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 - # 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 + """>>> lst = ['sv.add 1.v, 5, 9.v' ] + + adds: + * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 + * 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 + """ isa = SVP64Asm(['sv.add 1.v, 5, 9.v' ]) lst = list(isa) @@ -129,8 +144,11 @@ class DecoderTestCase(FHDLTestCase): self._check_regs(sim, expected_regs) def test_sv_add_vl_0(self): - # adds: - # none because VL is zer0 + """>>> lst = ['sv.add 1, 5.v, 9.v' + ] + adds: + * none because VL is zero + """ isa = SVP64Asm(['sv.add 1, 5.v, 9.v' ]) lst = list(isa) @@ -155,9 +173,13 @@ class DecoderTestCase(FHDLTestCase): self._check_regs(sim, expected_regs) def test_sv_add_cr(self): - # adds when Rc=1: TODO CRs higher up - # 1 = 5 + 9 => 0 = -1+1 CR0=0b100 - # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 + """>>> lst = ['sv.add. 1.v, 5.v, 9.v' + ] + + adds when Rc=1: TODO CRs higher up + * 1 = 5 + 9 => 0 = -1+1 CR0=0b100 + * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 + """ isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v' ]) lst = list(isa) -- 2.30.2