From 02f9239ecaa18958b6490d3b921b9b322bbe635a Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Fri, 29 Oct 2021 18:42:02 +0200 Subject: [PATCH] periph: conform with nmigen-soc breaking changes. * use window names for CSR banks and bus interfaces. * do not assign a memory map at window creation (doing so would freeze the memory map) * use ResourceInfo when dumping resources. --- lambdasoc/cores/litedram.py | 5 +++-- lambdasoc/periph/base.py | 45 ++++++++++++++++++++----------------- lambdasoc/periph/event.py | 6 ++--- lambdasoc/periph/sdram.py | 42 +++++++++++++++++++++++++--------- lambdasoc/periph/sram.py | 7 +++--- lambdasoc/soc/base.py | 14 +++++------- 6 files changed, 71 insertions(+), 48 deletions(-) diff --git a/lambdasoc/cores/litedram.py b/lambdasoc/cores/litedram.py index c1515b4..497112f 100644 --- a/lambdasoc/cores/litedram.py +++ b/lambdasoc/cores/litedram.py @@ -426,7 +426,7 @@ class Core(Elaboratable): data_width = config.user_data_width, ) user_map = MemoryMap(addr_width=user_addr_width, data_width=8) - user_map.add_resource("user_port_0", size=size) + user_map.add_resource(object(), name="user_port_0", size=size) self.user_port.memory_map = user_map self._ctrl_bus = None @@ -470,7 +470,8 @@ class Core(Elaboratable): res_type, res_name, addr, size, attrs = row if res_type == "csr_register": ctrl_map.add_resource( - res_name, + object(), + name = res_name, addr = int(addr, 16), size = int(size, 10) * self.config.csr_data_width // ctrl_map.data_width, extend = True, diff --git a/lambdasoc/periph/base.py b/lambdasoc/periph/base.py index b023ad5..97701d2 100644 --- a/lambdasoc/periph/base.py +++ b/lambdasoc/periph/base.py @@ -118,11 +118,13 @@ class Peripheral: .format(irq)) self._irq = irq - def csr_bank(self, *, addr=None, alignment=None): + def csr_bank(self, *, name=None, addr=None, alignment=None): """Request a CSR bank. Arguments --------- + name : str + Optional. Bank name. addr : int or None Address of the bank. If ``None``, the implicit next address will be used. Otherwise, the exact specified address (which must be a multiple of @@ -135,12 +137,12 @@ class Peripheral: ------------ An instance of :class:`CSRBank`. """ - bank = CSRBank(name_prefix=self.name) + bank = CSRBank(name=name) self._csr_banks.append((bank, addr, alignment)) return bank def window(self, *, addr_width, data_width, granularity=None, features=frozenset(), - alignment=0, addr=None, sparse=None): + name=None, addr=None, sparse=None): """Request a window to a subordinate bus. See :meth:`nmigen_soc.wishbone.Decoder.add` for details. @@ -150,10 +152,7 @@ class Peripheral: An instance of :class:`nmigen_soc.wishbone.Interface`. """ window = wishbone.Interface(addr_width=addr_width, data_width=data_width, - granularity=granularity, features=features) - granularity_bits = log2_int(data_width // window.granularity) - window.memory_map = MemoryMap(addr_width=addr_width + granularity_bits, - data_width=window.granularity, alignment=alignment) + granularity=granularity, features=features, name=name) self._windows.append((window, addr, sparse)) return window @@ -219,12 +218,15 @@ class CSRBank: Parameters ---------- - name_prefix : str - Name prefix of the bank registers. + name : str + Optional. Name prefix of the bank registers. """ - def __init__(self, *, name_prefix=""): - self._name_prefix = name_prefix - self._csr_regs = [] + def __init__(self, *, name=None): + if name is not None and not isinstance(name, str): + raise TypeError("Name must be a string, not {!r}".format(name)) + + self.name = name + self._csr_regs = [] def csr(self, width, access, *, addr=None, alignment=None, name=None, src_loc_at=0): @@ -252,10 +254,9 @@ class CSRBank: raise TypeError("Name must be a string, not {!r}".format(name)) name = name or tracer.get_var_name(depth=2 + src_loc_at).lstrip("_") - elem_name = "{}_{}".format(self._name_prefix, name) - if any(elem.name == elem_name for (elem, _, _) in self._csr_regs): - raise Exception("CSR \"{}\" has already been defined".format(elem_name)) - elem = csr.Element(width, access, name=elem_name) + if any(elem.name == name for (elem, _, _) in self._csr_regs): + raise Exception("CSR \"{}\" has already been defined".format(name)) + elem = csr.Element(width, access, name=name) self._csr_regs.append((elem, addr, alignment)) return elem @@ -306,14 +307,18 @@ class PeripheralBridge(Elaboratable): self._wb_decoder = wishbone.Decoder(addr_width=1, data_width=data_width, granularity=granularity, - features=features, alignment=alignment) + features=features, alignment=alignment, + name=periph.name) self._csr_subs = [] for bank, bank_addr, bank_alignment in periph.iter_csr_banks(): if bank_alignment is None: bank_alignment = alignment - csr_mux = csr.Multiplexer(addr_width=1, data_width=granularity, alignment=bank_alignment) + csr_mux = csr.Multiplexer( + addr_width=1, data_width=granularity, alignment=bank_alignment, + name=bank.name, + ) for elem, elem_addr, elem_alignment in bank.iter_csr_regs(): if elem_alignment is None: elem_alignment = alignment @@ -328,10 +333,10 @@ class PeripheralBridge(Elaboratable): events = list(periph.iter_events()) if len(events) > 0: - self._int_src = InterruptSource(events, name="{}_ev".format(periph.name)) + self._int_src = InterruptSource(events, name=periph.name) self.irq = self._int_src.irq - csr_mux = csr.Multiplexer(addr_width=1, data_width=8, alignment=alignment) + csr_mux = csr.Multiplexer(addr_width=1, data_width=8, alignment=alignment, name="ev") csr_mux.add(self._int_src.status, extend=True) csr_mux.add(self._int_src.pending, extend=True) csr_mux.add(self._int_src.enable, extend=True) diff --git a/lambdasoc/periph/event.py b/lambdasoc/periph/event.py index 87b631f..6d8d5f6 100644 --- a/lambdasoc/periph/event.py +++ b/lambdasoc/periph/event.py @@ -95,9 +95,9 @@ class InterruptSource(Elaboratable): self._events = list(events) width = len(events) - self.status = csr.Element(width, "r", name="{}_status".format(self.name)) - self.pending = csr.Element(width, "rw", name="{}_pending".format(self.name)) - self.enable = csr.Element(width, "rw", name="{}_enable".format(self.name)) + self.status = csr.Element(width, "r", name="status") + self.pending = csr.Element(width, "rw", name="pending") + self.enable = csr.Element(width, "rw", name="enable") self.irq = IRQLine(name="{}_irq".format(self.name)) diff --git a/lambdasoc/periph/sdram.py b/lambdasoc/periph/sdram.py index 5d8380b..c044f89 100644 --- a/lambdasoc/periph/sdram.py +++ b/lambdasoc/periph/sdram.py @@ -269,34 +269,54 @@ class SDRAMPeripheral(Peripheral, Elaboratable): .format(core)) self.core = core - data_width = core.ctrl_bus.data_width - granularity = core.ctrl_bus.granularity + data_width = core.ctrl_bus.data_width + granularity = core.ctrl_bus.granularity + granularity_bits = log2_int(data_width // granularity) + + # Data path : bridge -> cache -> LiteDRAM user port self._data_bus = self.window( addr_width = core.user_port.addr_width + log2_int(core.user_port.data_width // 8) - - log2_int(data_width // granularity), + - granularity_bits, data_width = data_width, granularity = granularity, features = {"cti", "bte"}, ) - self._ctrl_bus = self.window( - addr_width = core._ctrl_bus.addr_width, - data_width = core._ctrl_bus.data_width, - granularity = core._ctrl_bus.granularity, - addr = core.size, + data_map = MemoryMap( + addr_width = self._data_bus.addr_width + granularity_bits, + data_width = granularity, + alignment = 0, ) - self._cache = WritebackCache( + self._cache = WritebackCache( core.user_port, size = cache_size, data_width = data_width, granularity = granularity, dirty_init = cache_dirty_init, ) + data_map.add_window(self._cache.intr_bus.memory_map) + + self._data_bus.memory_map = data_map + + # Control path : bridge -> LiteDRAM control port + + self._ctrl_bus = self.window( + addr_width = core._ctrl_bus.addr_width, + data_width = data_width, + granularity = granularity, + addr = core.size, + ) + ctrl_map = MemoryMap( + addr_width = self._ctrl_bus.addr_width + granularity_bits, + data_width = granularity, + alignment = 0, + ) + + ctrl_map.add_window(core.ctrl_bus.memory_map) - self._ctrl_bus.memory_map.add_window(core.ctrl_bus.memory_map) - self._data_bus.memory_map.add_window(self._cache.intr_bus.memory_map) + self._ctrl_bus.memory_map = ctrl_map self._bridge = self.bridge(data_width=data_width, granularity=granularity) self.bus = self._bridge.bus diff --git a/lambdasoc/periph/sram.py b/lambdasoc/periph/sram.py index a21ab91..b69769f 100644 --- a/lambdasoc/periph/sram.py +++ b/lambdasoc/periph/sram.py @@ -42,15 +42,14 @@ class SRAMPeripheral(Peripheral, Elaboratable): "of {} ({} / {})" .format(size, data_width // granularity, data_width, granularity)) - self._mem = Memory(depth=(size * granularity) // data_width, width=data_width, - name=self.name) + self._mem = Memory(depth=(size * granularity) // data_width, width=data_width) self.bus = wishbone.Interface(addr_width=log2_int(self._mem.depth), data_width=self._mem.width, granularity=granularity, features={"cti", "bte"}) - map = MemoryMap(addr_width=log2_int(size), data_width=granularity) - map.add_resource(self._mem, size=size) + map = MemoryMap(addr_width=log2_int(size), data_width=granularity, name=self.name) + map.add_resource(self._mem, name="mem", size=size) self.bus.memory_map = map self.size = size diff --git a/lambdasoc/soc/base.py b/lambdasoc/soc/base.py index c9a381e..593d44e 100644 --- a/lambdasoc/soc/base.py +++ b/lambdasoc/soc/base.py @@ -129,8 +129,8 @@ class ConfigBuilder: "{{name}}_resources.csv": r""" # {{autogenerated}} # , , , - {% for resource, (start, end, width) in soc.memory_map.all_resources() -%} - {{resource.name}}, {{hex(start)}}, {{hex(end)}}, {{width}} + {% for res_info in soc.memory_map.all_resources() -%} + {{"_".join(res_info.name)}}, {{hex(res_info.start)}}, {{hex(res_info.end)}}, {{res_info.width}} {% endfor %} """, } @@ -149,12 +149,10 @@ class ConfigBuilder: return start raise KeyError(periph) - def periph_csrs(periph): + def periph_size(periph): assert isinstance(periph, Peripheral) - periph_map = periph.bus.memory_map - for resource, (start, end, width) in periph_map.all_resources(): - if isinstance(resource, csr.Element): - yield resource, (start, end, width) + granularity_bits = log2_int(periph.bus.data_width // periph.bus.granularity) + return 2**(periph.bus.addr_width + granularity_bits) def emit_commands(): commands = [] @@ -178,7 +176,7 @@ class ConfigBuilder: "hex": hex, "name": name, "periph_addr": periph_addr, - "periph_csrs": periph_csrs, + "periph_size": periph_size, "soc": soc, "software_dir": os.path.dirname(software.__file__), **render_params, -- 2.30.2