From 034156f3affca12c66abf53d25003a8b9991a51d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 12:31:38 +0100 Subject: [PATCH] update docstring on simple/core.py --- src/soc/simple/core.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 87834358..ec8b05f9 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -3,7 +3,22 @@ not in any way intended for production use. connects up FunctionUnits to Register Files in a brain-dead fashion that only permits one and only one Function Unit to be operational. + +the principle here is to take the Function Units, analyse their regspecs, +and turn their requirements for access to register file read/write ports +into groupings by Register File and Register File Port name. + +under each grouping - by regfile/port - a list of Function Units that +need to connect to that port is created. as these are a contended +resource a "Broadcast Bus" per read/write port is then also created, +with access to it managed by a PriorityPicker. + +the brain-dead part of this module is that even though there is no +conflict of access, regfile read/write hazards are *not* analysed, +and consequently it is safer to wait for the Function Unit to complete +before allowing a new instruction to proceed. """ + from nmigen import Elaboratable, Module, Signal from nmigen.cli import rtlil -- 2.30.2