From 0358055a338a368e2457859f47664ffb9bc6d72e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 13 May 2020 22:40:12 +0100 Subject: [PATCH] update comment on Logical pipeline --- src/soc/logical/main_stage.py | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/soc/logical/main_stage.py b/src/soc/logical/main_stage.py index b88649d8..18a33299 100644 --- a/src/soc/logical/main_stage.py +++ b/src/soc/logical/main_stage.py @@ -1,8 +1,10 @@ -# This stage is intended to do most of the work of executing the ALU -# instructions. This would be like the additions, logical operations, -# and shifting, as well as carry and overflow generation. This module -# however should not gate the carry or overflow, that's up to the -# output stage +# This stage is intended to do most of the work of executing Logical +# instructions. This is OR, AND and XOR, however input and output +# stages also perform bit-negation on input(s) and output, as well as +# carry and overflow generation. +# This module however should not gate the carry or overflow, that's up +# to the output stage + from nmigen import (Module, Signal, Cat, Repl, Mux, Const) from nmutil.pipemodbase import PipeModBase from soc.logical.pipe_data import ALUInputData @@ -26,18 +28,13 @@ class LogicalMainStage(PipeModBase): comb = m.d.comb ########################## - # main switch-statement for handling arithmetic and logic operations + # main switch-statement for handling logic operations AND, OR and XOR with m.Switch(self.i.ctx.op.insn_type): - #### and #### with m.Case(InternalOp.OP_AND): comb += self.o.o.eq(self.i.a & self.i.b) - - #### or #### with m.Case(InternalOp.OP_OR): comb += self.o.o.eq(self.i.a | self.i.b) - - #### xor #### with m.Case(InternalOp.OP_XOR): comb += self.o.o.eq(self.i.a ^ self.i.b) -- 2.30.2