From 035f778121c179e0712e6c81f19195d0ab2c2f35 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 6 Apr 2018 14:37:43 +0200 Subject: [PATCH] Add documentation for anyconst/anyseq/allconst/allseq attribute Signed-off-by: Clifford Wolf --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index 514d8e2f7..2a7a3b6ee 100644 --- a/README.md +++ b/README.md @@ -402,6 +402,10 @@ Non-standard or SystemVerilog features for formal verification statements it is sufficient if just one ``$allconst/$allseq`` value triggers the property (similar to ``$anyconst/$anyseq``). +- Wires/registers decalred using the ``anyconst/anyseq/allconst/allseq`` attribute + (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven + by a ``$anyconst/$anyseq/$allconst/$allseq`` function. + - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are supported in any clocked block. -- 2.30.2