From 0367433a2a41a3718a06862ef0c2ca6cf5c9003a Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 8 May 2022 16:56:23 +0100
Subject: [PATCH]

---
 openpower/sv/SimpleV_rationale.mdwn | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 4afb0c392..85116aced 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -241,13 +241,13 @@ of magnitude increase in the number of hand-written lines of assembler
 compared to a well-designed Cray-style Vector ISA with a `setvl`
 instruction.
 
-<blockquote>
-*Packed SIMD looped algorithms actually have to
+*<blockquote>
+Packed SIMD looped algorithms actually have to
 contain multiple implementations processing fragments of data at
 different SIMD widths: Cray-style Vectors have just the one, covering not
 just current architectural implementations but future ones with
-wider back-end ALUs as well.*
-</blockquote>
+wider back-end ALUs as well.
+</blockquote>*
 
 Assuming then that variable-length Vectors are obviously desirable,
 it becomes a matter of how, not if.  Both Cray and NEC SX Aurora
-- 
2.30.2