From 0371519c3977fcf4ffc71315cb9e0aae3ee967a2 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 10 Jul 2018 12:51:02 +0200 Subject: [PATCH] Added Monitor class that can monitor all changes in a Design or in a Module --- kernel/python_wrappers.cc | 119 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 04aebb1b8..4ba2a1185 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -1,6 +1,10 @@ #ifdef WITH_PYTHON #include "yosys.h" +#include +#include +#include +#include #include namespace YOSYS_PYTHON { @@ -9,6 +13,7 @@ namespace YOSYS_PYTHON { struct Module; struct Cell; struct Wire; + struct Monitor; void yosys_setup() { @@ -116,6 +121,8 @@ namespace YOSYS_PYTHON { } return result; } + + void register_monitor(Monitor* const m); }; std::ostream &operator<<(std::ostream &ostr, const Module &module) @@ -168,8 +175,113 @@ namespace YOSYS_PYTHON { if(cpp_design != NULL) Yosys::run_pass(command, cpp_design); } + + void register_monitor(Monitor* const m); }; + struct Monitor : public Yosys::RTLIL::Monitor + { + + virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_add(new Module(module)); + } + + virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_del(new Module(module)); + } + + virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE + { + //log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE + { + //log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + { + //log("#TRACE# New connections in module %s:\n", log_id(module)); + //for (auto &sigsig : sigsig_vec) + // log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); + } + + virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_blackout(new Module(module)); + } + + //virtual void notify_connect(Cell*, const Yosys::RTLIL::IdString&, const Yosys::RTLIL::SigSpec&, Yosys::RTLIL::SigSpec&) { } + //virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } + //virtual void notify_connect(RTLIL::Module*, const std::vector&) { } + + virtual void py_notify_module_add(Module*){}; + virtual void py_notify_module_del(Module*){}; + virtual void py_notify_blackout(Module*){}; + + }; + + struct MonitorWrap : Monitor, boost::python::wrapper + { + void py_notify_module_add(Module* m) + { + if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) + py_notify_module_add(m); + else + Monitor::py_notify_module_add(m); + } + + void default_py_notify_module_add(Module* m) + { + this->Monitor::py_notify_module_add(m); + } + + void py_notify_module_del(Module* m) + { + if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) + py_notify_module_del(m); + else + Monitor::py_notify_module_del(m); + } + + void default_py_notify_module_del(Module* m) + { + this->Monitor::py_notify_module_del(m); + } + + void py_notify_blackout(Module* m) + { + if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) + py_notify_blackout(m); + else + Monitor::py_notify_blackout(m); + } + + void default_py_notify_blackout(Module* m) + { + this->Monitor::py_notify_blackout(m); + } + }; + + void Design::register_monitor(Monitor* const m) + { + Yosys::RTLIL::Design* cpp_design = this->get_cpp_obj(); + if(cpp_design == NULL) + return; + cpp_design->monitors.insert(m); + } + + void Module::register_monitor(Monitor* const m) + { + Yosys::RTLIL::Module* cpp_design = this->get_cpp_obj(); + if(cpp_design == NULL) + return; + cpp_design->monitors.insert(m); + } + std::ostream &operator<<(std::ostream &ostr, const Design &design) { ostr << "Design with id " << design.hashid; @@ -196,6 +308,7 @@ namespace YOSYS_PYTHON { .def(init<>()) .def("get_modules", &Design::get_modules) .def("run",&Design::run) + .def("register_monitor", &Design::register_monitor) ; class_("Module", no_init) @@ -203,6 +316,7 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def("get_cells", &Module::get_cells) .def("get_wires", &Module::get_wires) + .def("register_monitor", &Module::register_monitor) ; class_("Cell", no_init) @@ -215,6 +329,11 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; + class_("Monitor") + .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) + .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) + .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) + ; def("yosys_setup",yosys_setup); def("run",run); -- 2.30.2