From 03b289a851c62eb2a7e3592432876bfa8a56770b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 11:38:52 -0700 Subject: [PATCH] Add 'cinput' and 'coutput' to symbols file for boxes --- backends/aiger/xaiger.cc | 58 +++++++++++++++-------------------- frontends/aiger/aigerparse.cc | 35 +++++++++++++++++++++ passes/techmap/abc9.cc | 25 ++++++++++----- 3 files changed, 77 insertions(+), 41 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 6cf0cb026..582e8e076 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -49,7 +49,8 @@ struct XAigerWriter dict not_map, ff_map, alias_map; dict> and_map; //pool initstate_bits; - vector> ci_bits, co_bits; + vector> ci_bits; + vector> co_bits; vector> aig_gates; vector aig_latchin, aig_latchinit, aig_outputs; @@ -327,6 +328,7 @@ struct XAigerWriter // Box ordering is alphabetical cell->connections_.sort(RTLIL::sort_by_id_str()); for (const auto &c : cell->connections()) { + int offset = 0; for (auto b : c.second.bits()) { auto is_input = cell->input(c.first); auto is_output = cell->output(c.first); @@ -335,11 +337,11 @@ struct XAigerWriter SigBit I = sigmap(b); if (I != b) alias_map[b] = I; - co_bits.emplace_back(b, 0); + co_bits.emplace_back(b, cell, c.first, offset++, 0); } if (is_output) { SigBit O = sigmap(b); - ci_bits.emplace_back(O, 0); + ci_bits.emplace_back(O, cell, c.first, offset++); } } } @@ -380,7 +382,7 @@ struct XAigerWriter // Do some CI/CO post-processing: // CIs cannot be undriven for (const auto &c : ci_bits) - undriven_bits.erase(c.first); + undriven_bits.erase(std::get<0>(c)); // Erase all POs that are undriven if (!holes_mode) for (auto bit : undriven_bits) @@ -399,18 +401,13 @@ struct XAigerWriter init_map.sort(); if (holes_mode) { -#ifndef NDEBUG - RTLIL::SigBit last_bit; - for (auto bit : input_bits) { - log_assert(!last_bit.wire || last_bit.wire->port_id < bit.wire->port_id); - last_bit = bit; - } - last_bit = RTLIL::SigBit(); - for (auto bit : output_bits) { - log_assert(!last_bit.wire || last_bit.wire->port_id < bit.wire->port_id); - last_bit = bit; - } -#endif + struct sort_by_port_id { + bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const { + return a.wire->port_id < b.wire->port_id; + } + }; + input_bits.sort(sort_by_port_id()); + output_bits.sort(sort_by_port_id()); } else { input_bits.sort(); @@ -431,8 +428,7 @@ struct XAigerWriter for (auto &c : ci_bits) { aig_m++, aig_i++; - c.second = 2*aig_m; - aig_map[c.first] = c.second; + aig_map[std::get<0>(c)] = 2*aig_m; } if (imode && input_bits.empty()) { @@ -496,9 +492,9 @@ struct XAigerWriter // aig_latchin.push_back(1); for (auto &c : co_bits) { - RTLIL::SigBit bit = c.first; - c.second = aig_o++; - ordered_outputs[bit] = c.second; + RTLIL::SigBit bit = std::get<0>(c); + std::get<4>(c) = aig_o++; + ordered_outputs[bit] = std::get<4>(c); aig_outputs.push_back(bit2aig(bit)); } @@ -774,8 +770,7 @@ struct XAigerWriter //Pass::call(holes_module->design, "techmap"); Pass::call(holes_module->design, "aigmap"); - //TODO: clean will mess up port_ids - //Pass::call(holes_module->design, "clean -purge"); + Pass::call(holes_module->design, "clean -purge"); holes_module->design->selection_stack.pop_back(); @@ -880,22 +875,17 @@ struct XAigerWriter } for (const auto &c : ci_bits) { - RTLIL::SigBit b = c.first; - RTLIL::Wire *wire = b.wire; - int i = b.offset; + RTLIL::SigBit b = std::get<0>(c); + int i = std::get<3>(c); int a = bit2aig(b); log_assert((a & 1) == 0); - input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); + input_lines[a] += stringf("cinput %d %d %s %s\n", (a >> 1)-1, i, log_id(std::get<1>(c)), log_id(std::get<2>(c))); } for (const auto &c : co_bits) { - RTLIL::SigBit b = c.first; - RTLIL::Wire *wire = b.wire; - int o = c.second; - if (wire) - output_lines[o] += stringf("output %d %d %s\n", o, b.offset, log_id(wire)); - else - output_lines[o] += stringf("output %d %d __const%d__\n", o, 0, b.data); + int i = std::get<3>(c); + int o = std::get<4>(c); + output_lines[o] += stringf("coutput %d %d %s %s\n", o, i, log_id(std::get<1>(c)), log_id(std::get<2>(c))); } input_lines.sort(); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 94bfdfa3e..2441ee937 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -704,6 +704,41 @@ void AigerReader::post_process() } } } + else if (type == "cinput" || type == "coutput") { + RTLIL::Wire* wire; + if (type == "cinput") { + log_assert(static_cast(variable) < inputs.size()); + wire = inputs[variable]; + log_assert(wire); + log_assert(wire->port_input); + } + else if (type == "coutput") { + log_assert(static_cast(variable) < outputs.size()); + wire = outputs[variable]; + log_assert(wire); + log_assert(wire->port_output); + } + else log_abort(); + + std::string port; + mf >> port; + RTLIL::IdString cell_name = RTLIL::escape_id(symbol); + RTLIL::IdString cell_port = RTLIL::escape_id(port); + + RTLIL::Cell* cell = module->cell(cell_name); + if (!cell) + cell = module->addCell(cell_name, "$__blackbox__"); + wire->port_input = false; + wire->port_output = false; + if (cell->hasPort(cell_port)) { + log_assert(index == GetSize(cell->getPort(cell_port))); + cell->connections_[cell_port].append(wire); + } + else { + log_assert(index == 0); + cell->setPort(cell_port, wire); + } + } else log_error("Symbol type '%s' not recognised.\n", type.c_str()); } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8341741fa..89e3eb948 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -786,14 +786,24 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri continue; } - if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) { - SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]; - SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]; - module->connect(my_y, my_a); - continue; + RTLIL::Cell* cell; + if (c->type == "$lut") { + if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) { + SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]; + SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]; + module->connect(my_y, my_a); + continue; + } + else { + cell = module->addCell(remap_name(c->name), c->type); + } + } + else { + cell = module->cell(c->name); + log_assert(cell); + log_assert(c->type == "$__blackbox__"); } - RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type); if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; cell->parameters = c->parameters; for (auto &conn : c->connections()) { @@ -802,7 +812,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (c.width == 0) continue; //log_assert(c.width == 1); - c.wire = module->wires_[remap_name(c.wire->name)]; + if (c.wire) + c.wire = module->wires_[remap_name(c.wire->name)]; newsig.append(c); } cell->setPort(conn.first, newsig); -- 2.30.2