From 03c9044c2edf8301779fe5d0173d7e6d1e7ee1c2 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 21 May 2012 09:13:33 -0700 Subject: [PATCH] i915: Drop gen4+ code from the forked clear code. Reviewed-by: Ian Romanick Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i915/intel_clear.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i915/intel_clear.c b/src/mesa/drivers/dri/i915/intel_clear.c index 331635148f6..96d9c8fe682 100644 --- a/src/mesa/drivers/dri/i915/intel_clear.c +++ b/src/mesa/drivers/dri/i915/intel_clear.c @@ -89,9 +89,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask) struct intel_renderbuffer *irb; int i; - if (!_mesa_check_conditional_render(ctx)) - return; - if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) { intel->front_buffer_dirty = true; } @@ -116,7 +113,7 @@ intelClear(struct gl_context *ctx, GLbitfield mask) } /* HW color buffers (front, back, aux, generic FBO, etc) */ - if (intel->gen < 6 && colorMask == ~0) { + if (colorMask == ~0) { /* clear all R,G,B,A */ blit_mask |= (mask & BUFFER_BITS_COLOR); } @@ -143,12 +140,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask) */ tri_mask |= BUFFER_BIT_STENCIL; } - else if (intel->has_separate_stencil && - stencilRegion->tiling == I915_TILING_NONE) { - /* The stencil buffer is actually W tiled, which the hardware - * cannot blit to. */ - tri_mask |= BUFFER_BIT_STENCIL; - } else { /* clearing all stencil bits, use blitting */ blit_mask |= BUFFER_BIT_STENCIL; -- 2.30.2