From 03d2ba082512c16a06b0de5b974791b2d1e8965b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 28 Jun 2018 10:09:24 +0100 Subject: [PATCH] corrections to predicate fn --- simple_v_extension/simple_v_chennai_2018.tex | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index bc69edf9e..902f7cc22 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -370,9 +370,9 @@ for (i = 0; i < 16; i++) // 16 CSRs? \begin{semiverbatim} def get\_pred\_val(bool is\_fp\_op, int reg): tb = int\_pred if is\_fp\_op else fp\_pred - if (!tb[reg].enabled): - return ~0x0 // all ops enabled - predidx = tb[reg].predidx // redirection occurs HERE + if (!tb[reg].enabled): return ~0x0 // all ops enabled + predidx = tb[reg].predidx // redirection occurs HERE + predidx += tb[reg].bank << 5 // 0 (1=rsvd) predicate = intreg[predidx] // actual predicate HERE if (tb[reg].inv): predicate = ~predicate // invert ALL bits -- 2.30.2