From 03d6fa351062873348c9b8c7a066cbb79468a1a0 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Sun, 18 Sep 2022 12:07:17 +0300 Subject: [PATCH] power_insn: support svm specifier --- src/openpower/decoder/power_insn.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index ca68f9fc..e258bb1f 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1349,6 +1349,13 @@ class NormalSubvectorReduceRM(NormalBaseRM): """normal: subvector reduce mode, SUBVL>1""" SVM: BaseRM.mode[3] + @property + def specifiers(self): + if self.SVM: + yield "svm" + + yield from super().specifiers + class NormalReservedRM(NormalBaseRM): """normal: reserved""" @@ -1645,6 +1652,9 @@ class CROpSubvectorReduceRM(CROpBaseRM): def specifiers(self): if self.zz: yield f"zz" + if self.SVM: + yield "svm" + yield from super().specifiers -- 2.30.2