From 03da82838b7ef81385c069ca906d4f414dd545fa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 12 Jul 2018 09:57:18 +0100 Subject: [PATCH] add slids --- shakti/m_class/libre_riscv_chennai_2018.tex | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex index eac12c3d5..0a7e621f5 100644 --- a/shakti/m_class/libre_riscv_chennai_2018.tex +++ b/shakti/m_class/libre_riscv_chennai_2018.tex @@ -284,8 +284,8 @@ \frame{\frametitle{Challenging Stuff [4] - Power Management} \begin{itemize} - \item Been done before, but not as a Libre Design. - \item Sanjay Charagulla: GlobalFoundries, 22nm mobile process + \item Been done before (many times), but not as a Libre Design. + \item Sanjay Charagulla: GlobalFoundries 22nm mobile process can reach as low as 0.4v \item GPIO Banks need per-bank VREF (1.8v? to 3.3v)\\ IO pads need built-in @@ -298,7 +298,7 @@ \end{itemize} {\it Really need help. PLLs, Analog stuff: specific domain expertise. Fall-back example: - https://www.dolphin-integration.com. + https://www.dolphin-integration.com? } } -- 2.30.2