From 03dbf9de756a6e3325432b10440db1a1dc305f80 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 9 Oct 2018 01:35:57 +0100 Subject: [PATCH] add example --- llvm_vector_backend.mdwn | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/llvm_vector_backend.mdwn b/llvm_vector_backend.mdwn index e7814becf..2393082d7 100644 --- a/llvm_vector_backend.mdwn +++ b/llvm_vector_backend.mdwn @@ -17,6 +17,7 @@ Examples: ARF1 = 0x01009005 ARF2 = 0x0100a006 + ARF3 = 0x0100b008 These would indicate that when the (virtual) register ARF1 is used, it is of type "integer", and it requires the reservation of the **real** @@ -32,6 +33,21 @@ registers 5 through 9 at the hardware level. align: 4; // an aligment restriction, in powers of 2. } BRC; +Examples: + + A Compressed instruction from SV has restrictions on the + range it may cover (unless redirection is taken into account). + It is also possible to specify a bitwidth of 16, and if that is + done, alignment has to be restricted to 4. So: + + brc1 = { + arf = 0x0100b008; // integer register, using "real" regs 8-11 inclusive + min = 8; // C-type instructions go from 8-15 in the opcode + max = 15; + size = 0x1 // 1=16-bit (?) + align: 2 // 2= 1<<2 (=4) because the "real" regs are 64-bit. + }; + ## Register Class Unions Register Classes are the union of multiple Base Register Classes -- 2.30.2