From 03e8b3551cf52b6b8b8efb48af7f413ddc4116b1 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Marcin=20=C5=9Alusarz?= <marcin.slusarz@intel.com>
Date: Thu, 9 Jul 2020 20:54:41 +0200
Subject: [PATCH] intel/perf: fix how pipeline stats are stored
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It matters only when counters are not ordered by offset.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5788>
---
 src/intel/perf/gen_perf_query.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/perf/gen_perf_query.c b/src/intel/perf/gen_perf_query.c
index 755ec9a83dd..3d4f922b2b3 100644
--- a/src/intel/perf/gen_perf_query.c
+++ b/src/intel/perf/gen_perf_query.c
@@ -625,7 +625,7 @@ snapshot_statistics_registers(struct gen_perf_context *ctx,
 
       perf->vtbl.store_register_mem(ctx->ctx, obj->pipeline_stats.bo,
                                     counter->pipeline_stat.reg, 8,
-                                    offset_in_bytes + i * sizeof(uint64_t));
+                                    offset_in_bytes + counter->offset);
    }
 }
 
-- 
2.30.2