From 03f66e8a8f77e2df4ecdc9b32bcc96ab5cb0e85e Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 31 Jul 2012 21:38:54 +0000 Subject: [PATCH] include/opcode/ * mips.h: Document microMIPS DSP ASE usage. (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for microMIPS DSP ASE support. (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. gas/ * config/tc-mips.c (macro_build) <'2'>: Handle microMIPS. (macro) : Update error handling. (validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases. <'7', '8', '0', '@', '^'>: Likewise. (mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS. <'9'>: Fix formatting. <'0', '@'>: Handle microMIPS. <'^'>: New case. gas/testsuite/ * gas/mips/micromips@mips32-dsp.d: New. * gas/mips/micromips@mips32-dspr2.d: New. * gas/mips/mips32-dsp.d: Remove -mips32r2. * gas/mips/mips32-dspr2.d: Likewise. * gas/mips/mips.exp: (mips_create_arch): Use -mips64r2 for micromips. Use run_dump_test_arches to run dsp tests. opcodes/ * micromips-opc.c (WR_a, RD_a, MOD_a): New macros. (DSP_VOLA): Likewise. (D32, D33): Likewise. (micromips_opcodes): Add DSP ASE instructions. * micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases. <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise. --- gas/ChangeLog | 13 + gas/config/tc-mips.c | 259 +++++++++++------- gas/testsuite/ChangeLog | 10 + gas/testsuite/gas/mips/micromips@mips32-dsp.d | 148 ++++++++++ .../gas/mips/micromips@mips32-dspr2.d | 74 +++++ gas/testsuite/gas/mips/mips.exp | 6 +- gas/testsuite/gas/mips/mips32-dsp.d | 2 +- gas/testsuite/gas/mips/mips32-dsp.s | 1 + gas/testsuite/gas/mips/mips32-dspr2.d | 2 +- gas/testsuite/gas/mips/mips32-dspr2.s | 1 + include/opcode/ChangeLog | 15 + include/opcode/mips.h | 50 ++-- opcodes/ChangeLog | 11 + opcodes/micromips-opc.c | 172 ++++++++++++ opcodes/mips-dis.c | 42 +++ 15 files changed, 686 insertions(+), 120 deletions(-) create mode 100644 gas/testsuite/gas/mips/micromips@mips32-dsp.d create mode 100644 gas/testsuite/gas/mips/micromips@mips32-dspr2.d diff --git a/gas/ChangeLog b/gas/ChangeLog index be74ff1ee6e..3baf0c71f36 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,16 @@ +2012-07-31 Maciej W. Rozycki + Chao-Ying Fu + Catherine Moore + + * config/tc-mips.c (macro_build) <'2'>: Handle microMIPS. + (macro) : Update error handling. + (validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases. + <'7', '8', '0', '@', '^'>: Likewise. + (mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS. + <'9'>: Fix formatting. + <'0', '@'>: Handle microMIPS. + <'^'>: New case. + 2012-07-31 Jan Beulich * config/tc-i386.c (match_template): Adjust error message diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 4760c05d4b7..e2ecf5d557d 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -351,7 +351,8 @@ static int file_ase_smartmips; static int file_ase_dsp; #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ - || mips_opts.isa == ISA_MIPS64R2) + || mips_opts.isa == ISA_MIPS64R2 \ + || mips_opts.micromips) #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) @@ -360,7 +361,8 @@ static int file_ase_dsp; static int file_ase_dspr2; #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ - || mips_opts.isa == ISA_MIPS64R2) + || mips_opts.isa == ISA_MIPS64R2 \ + || mips_opts.micromips) /* True if -mmt was passed or implied by arguments passed on the command line (e.g., by -march). */ @@ -4898,8 +4900,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...) continue; case '2': - gas_assert (!mips_opts.micromips); - INSERT_OPERAND (0, BP, insn, va_arg (args, int)); + INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); continue; case 'n': @@ -6414,10 +6415,15 @@ macro (struct mips_cl_insn *ip) case 2: macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); break; - default: + case 1: + case 3: macro_build (NULL, "balign", "t,s,2", treg, sreg, (int) imm_expr.X_add_number); break; + default: + as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), + (unsigned long) imm_expr.X_add_number); + break; } break; @@ -10486,8 +10492,17 @@ validate_micromips_insn (const struct mips_opcode *opc) break; case '.': USE_BITS (OFFSET10); break; case '1': USE_BITS (STYPE); break; + case '2': USE_BITS (BP); break; + case '3': USE_BITS (SA3); break; + case '4': USE_BITS (SA4); break; + case '5': USE_BITS (IMM8); break; + case '6': USE_BITS (RS); break; + case '7': USE_BITS (DSPACC); break; + case '8': USE_BITS (WRDSP); break; + case '0': USE_BITS (DSPSFT); break; case '<': USE_BITS (SHAMT); break; case '>': USE_BITS (SHAMT); break; + case '@': USE_BITS (IMM10); break; case 'B': USE_BITS (CODE10); break; case 'C': USE_BITS (COPZ); break; case 'D': USE_BITS (FD); break; @@ -10502,6 +10517,7 @@ validate_micromips_insn (const struct mips_opcode *opc) case 'T': USE_BITS (FT); break; case 'V': USE_BITS (FS); break; case '\\': USE_BITS (3BITPOS); break; + case '^': USE_BITS (RD); break; case 'a': USE_BITS (TARGET); break; case 'b': USE_BITS (RS); break; case 'c': USE_BITS (CODE); break; @@ -10773,8 +10789,9 @@ mips_ip (char *str, struct mips_cl_insn *ip) return; break; - case '2': /* DSP 2-bit unsigned immediate in bit 11. */ - gas_assert (!mips_opts.micromips); + case '2': + /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS + code) or 14 (for microMIPS code). */ my_getExpression (&imm_expr, s); check_absolute_expr (ip, &imm_expr); if ((unsigned long) imm_expr.X_add_number != 1 @@ -10783,100 +10800,125 @@ mips_ip (char *str, struct mips_cl_insn *ip) as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), (unsigned long) imm_expr.X_add_number); } - INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number); + INSERT_OPERAND (mips_opts.micromips, + BP, *ip, imm_expr.X_add_number); imm_expr.X_op = O_absent; s = expr_end; continue; - case '3': /* DSP 3-bit unsigned immediate in bit 21. */ - gas_assert (!mips_opts.micromips); - my_getExpression (&imm_expr, s); - check_absolute_expr (ip, &imm_expr); - if (imm_expr.X_add_number & ~OP_MASK_SA3) - { - as_bad (_("DSP immediate not in range 0..%d (%lu)"), - OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); - } - INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number); - imm_expr.X_op = O_absent; - s = expr_end; + case '3': + /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS + code) or 21 (for microMIPS code). */ + { + unsigned long mask = (mips_opts.micromips + ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); + + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number > mask) + as_bad (_("DSP immediate not in range 0..%lu (%lu)"), + mask, (unsigned long) imm_expr.X_add_number); + INSERT_OPERAND (mips_opts.micromips, + SA3, *ip, imm_expr.X_add_number); + imm_expr.X_op = O_absent; + s = expr_end; + } continue; - case '4': /* DSP 4-bit unsigned immediate in bit 21. */ - gas_assert (!mips_opts.micromips); - my_getExpression (&imm_expr, s); - check_absolute_expr (ip, &imm_expr); - if (imm_expr.X_add_number & ~OP_MASK_SA4) - { - as_bad (_("DSP immediate not in range 0..%d (%lu)"), - OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); - } - INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number); - imm_expr.X_op = O_absent; - s = expr_end; + case '4': + /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS + code) or 21 (for microMIPS code). */ + { + unsigned long mask = (mips_opts.micromips + ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); + + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number > mask) + as_bad (_("DSP immediate not in range 0..%lu (%lu)"), + mask, (unsigned long) imm_expr.X_add_number); + INSERT_OPERAND (mips_opts.micromips, + SA4, *ip, imm_expr.X_add_number); + imm_expr.X_op = O_absent; + s = expr_end; + } continue; - case '5': /* DSP 8-bit unsigned immediate in bit 16. */ - gas_assert (!mips_opts.micromips); - my_getExpression (&imm_expr, s); - check_absolute_expr (ip, &imm_expr); - if (imm_expr.X_add_number & ~OP_MASK_IMM8) - { - as_bad (_("DSP immediate not in range 0..%d (%lu)"), - OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); - } - INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number); - imm_expr.X_op = O_absent; - s = expr_end; + case '5': + /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS + code) or 16 (for microMIPS code). */ + { + unsigned long mask = (mips_opts.micromips + ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); + + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number > mask) + as_bad (_("DSP immediate not in range 0..%lu (%lu)"), + mask, (unsigned long) imm_expr.X_add_number); + INSERT_OPERAND (mips_opts.micromips, + IMM8, *ip, imm_expr.X_add_number); + imm_expr.X_op = O_absent; + s = expr_end; + } continue; - case '6': /* DSP 5-bit unsigned immediate in bit 21. */ - gas_assert (!mips_opts.micromips); - my_getExpression (&imm_expr, s); - check_absolute_expr (ip, &imm_expr); - if (imm_expr.X_add_number & ~OP_MASK_RS) - { - as_bad (_("DSP immediate not in range 0..%d (%lu)"), - OP_MASK_RS, (unsigned long) imm_expr.X_add_number); - } - INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number); - imm_expr.X_op = O_absent; - s = expr_end; + case '6': + /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS + code) or 21 (for microMIPS code). */ + { + unsigned long mask = (mips_opts.micromips + ? MICROMIPSOP_MASK_RS : OP_MASK_RS); + + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number > mask) + as_bad (_("DSP immediate not in range 0..%lu (%lu)"), + mask, (unsigned long) imm_expr.X_add_number); + INSERT_OPERAND (mips_opts.micromips, + RS, *ip, imm_expr.X_add_number); + imm_expr.X_op = O_absent; + s = expr_end; + } continue; case '7': /* Four DSP accumulators in bits 11,12. */ - gas_assert (!mips_opts.micromips); - if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && - s[3] >= '0' && s[3] <= '3') + if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' + && s[3] >= '0' && s[3] <= '3') { regno = s[3] - '0'; s += 4; - INSERT_OPERAND (0, DSPACC, *ip, regno); + INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); continue; } else as_bad (_("Invalid dsp acc register")); break; - case '8': /* DSP 6-bit unsigned immediate in bit 11. */ - gas_assert (!mips_opts.micromips); - my_getExpression (&imm_expr, s); - check_absolute_expr (ip, &imm_expr); - if (imm_expr.X_add_number & ~OP_MASK_WRDSP) - { - as_bad (_("DSP immediate not in range 0..%d (%lu)"), - OP_MASK_WRDSP, - (unsigned long) imm_expr.X_add_number); - } - INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number); - imm_expr.X_op = O_absent; - s = expr_end; + case '8': + /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS + code) or 14 (for microMIPS code). */ + { + unsigned long mask = (mips_opts.micromips + ? MICROMIPSOP_MASK_WRDSP + : OP_MASK_WRDSP); + + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number > mask) + as_bad (_("DSP immediate not in range 0..%lu (%lu)"), + mask, (unsigned long) imm_expr.X_add_number); + INSERT_OPERAND (mips_opts.micromips, + WRDSP, *ip, imm_expr.X_add_number); + imm_expr.X_op = O_absent; + s = expr_end; + } continue; case '9': /* Four DSP accumulators in bits 21,22. */ gas_assert (!mips_opts.micromips); - if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && - s[3] >= '0' && s[3] <= '3') + if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' + && s[3] >= '0' && s[3] <= '3') { regno = s[3] - '0'; s += 4; @@ -10887,22 +10929,27 @@ mips_ip (char *str, struct mips_cl_insn *ip) as_bad (_("Invalid dsp acc register")); break; - case '0': /* DSP 6-bit signed immediate in bit 20. */ - gas_assert (!mips_opts.micromips); - my_getExpression (&imm_expr, s); - check_absolute_expr (ip, &imm_expr); - min_range = -((OP_MASK_DSPSFT + 1) >> 1); - max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; - if (imm_expr.X_add_number < min_range || - imm_expr.X_add_number > max_range) - { + case '0': + /* DSP 6-bit signed immediate in bit 16 (for standard MIPS + code) or 20 (for microMIPS code). */ + { + long mask = (mips_opts.micromips + ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); + + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + min_range = -((mask + 1) >> 1); + max_range = ((mask + 1) >> 1) - 1; + if (imm_expr.X_add_number < min_range + || imm_expr.X_add_number > max_range) as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), (long) min_range, (long) max_range, (long) imm_expr.X_add_number); - } - INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number); - imm_expr.X_op = O_absent; - s = expr_end; + INSERT_OPERAND (mips_opts.micromips, + DSPSFT, *ip, imm_expr.X_add_number); + imm_expr.X_op = O_absent; + s = expr_end; + } continue; case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ @@ -10939,19 +10986,35 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; case '@': /* DSP 10-bit signed immediate in bit 16. */ - gas_assert (!mips_opts.micromips); - my_getExpression (&imm_expr, s); - check_absolute_expr (ip, &imm_expr); - min_range = -((OP_MASK_IMM10 + 1) >> 1); - max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; - if (imm_expr.X_add_number < min_range || - imm_expr.X_add_number > max_range) - { + { + long mask = (mips_opts.micromips + ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); + + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + min_range = -((mask + 1) >> 1); + max_range = ((mask + 1) >> 1) - 1; + if (imm_expr.X_add_number < min_range + || imm_expr.X_add_number > max_range) as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), (long) min_range, (long) max_range, (long) imm_expr.X_add_number); - } - INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number); + INSERT_OPERAND (mips_opts.micromips, + IMM10, *ip, imm_expr.X_add_number); + imm_expr.X_op = O_absent; + s = expr_end; + } + continue; + + case '^': /* DSP 5-bit unsigned immediate in bit 11. */ + gas_assert (mips_opts.micromips); + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) + as_bad (_("DSP immediate not in range 0..%d (%lu)"), + MICROMIPSOP_MASK_RD, + (unsigned long) imm_expr.X_add_number); + INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); imm_expr.X_op = O_absent; s = expr_end; continue; diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 92d72d86445..83062340303 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2012-07-31 Catherine Moore + Maciej W. Rozycki + + * gas/mips/micromips@mips32-dsp.d: New. + * gas/mips/micromips@mips32-dspr2.d: New. + * gas/mips/mips32-dsp.d: Remove -mips32r2. + * gas/mips/mips32-dspr2.d: Likewise. + * gas/mips/mips.exp: (mips_create_arch): Use -mips64r2 + for micromips. Use run_dump_test_arches to run dsp tests. + 2012-07-31 H.J. Lu * gas/d30v/bittest.l: Updated. diff --git a/gas/testsuite/gas/mips/micromips@mips32-dsp.d b/gas/testsuite/gas/mips/micromips@mips32-dsp.d new file mode 100644 index 00000000000..26f111063fb --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@mips32-dsp.d @@ -0,0 +1,148 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS DSP ASE for MIPS32 +#as: -mdsp -32 +#source: mips32-dsp.s + +# Check MIPS DSP ASE for MIPS32 Instruction Assembly (microMIPS) + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 <[^>]*> 0041 000d addq\.ph zero,at,v0 +0+0004 <[^>]*> 0062 0c0d addq_s\.ph at,v0,v1 +0+0008 <[^>]*> 0083 1305 addq_s\.w v0,v1,a0 +0+000c <[^>]*> 00a4 18cd addu\.qb v1,a0,a1 +0+0010 <[^>]*> 00c5 24cd addu_s\.qb a0,a1,a2 +0+0014 <[^>]*> 00e6 2a0d subq\.ph a1,a2,a3 +0+0018 <[^>]*> 0107 360d subq_s\.ph a2,a3,t0 +0+001c <[^>]*> 0128 3b45 subq_s\.w a3,t0,t1 +0+0020 <[^>]*> 0149 42cd subu\.qb t0,t1,t2 +0+0024 <[^>]*> 016a 4ecd subu_s\.qb t1,t2,t3 +0+0028 <[^>]*> 018b 5385 addsc t2,t3,t4 +0+002c <[^>]*> 01ac 5bc5 addwc t3,t4,t5 +0+0030 <[^>]*> 01cd 6295 modsub t4,t5,t6 +0+0034 <[^>]*> 01ae f13c raddu\.w\.qb t5,t6 +0+0038 <[^>]*> 01cf 113c absq_s\.ph t6,t7 +0+003c <[^>]*> 01f0 213c absq_s\.w t7,s0 +0+0040 <[^>]*> 0251 80ad precrq\.qb\.ph s0,s1,s2 +0+0044 <[^>]*> 0272 88ed precrq\.ph\.w s1,s2,s3 +0+0048 <[^>]*> 0293 912d precrq_rs\.ph\.w s2,s3,s4 +0+004c <[^>]*> 02b4 996d precrqu_s\.qb\.ph s3,s4,s5 +0+0050 <[^>]*> 0295 513c preceq\.w\.phl s4,s5 +0+0054 <[^>]*> 02b6 613c preceq\.w\.phr s5,s6 +0+0058 <[^>]*> 02d7 713c precequ\.ph\.qbl s6,s7 +0+005c <[^>]*> 02f8 913c precequ\.ph\.qbr s7,t8 +0+0060 <[^>]*> 0319 733c precequ\.ph\.qbla t8,t9 +0+0064 <[^>]*> 033a 933c precequ\.ph\.qbra t9,k0 +0+0068 <[^>]*> 035b b13c preceu\.ph\.qbl k0,k1 +0+006c <[^>]*> 037c d13c preceu\.ph\.qbr k1,gp +0+0070 <[^>]*> 039d b33c preceu\.ph\.qbla gp,sp +0+0074 <[^>]*> 03be d33c preceu\.ph\.qbra sp,s8 +0+0078 <[^>]*> 03df 087c shll\.qb s8,ra,0x0 +0+007c <[^>]*> 03df e87c shll\.qb s8,ra,0x7 +0+0080 <[^>]*> 0001 fb95 shllv\.qb ra,zero,at +0+0084 <[^>]*> 0001 03b5 shll\.ph zero,at,0x0 +0+0088 <[^>]*> 0001 f3b5 shll\.ph zero,at,0xf +0+008c <[^>]*> 0043 0b8d shllv\.ph at,v0,v1 +0+0090 <[^>]*> 0043 0bb5 shll_s\.ph v0,v1,0x0 +0+0094 <[^>]*> 0043 fbb5 shll_s\.ph v0,v1,0xf +0+0098 <[^>]*> 0085 1f8d shllv_s\.ph v1,a0,a1 +0+009c <[^>]*> 0085 03f5 shll_s\.w a0,a1,0x0 +0+00a0 <[^>]*> 0085 fbf5 shll_s\.w a0,a1,0x1f +0+00a4 <[^>]*> 00c7 2bd5 shllv_s\.w a1,a2,a3 +0+00a8 <[^>]*> 00c7 187c shrl\.qb a2,a3,0x0 +0+00ac <[^>]*> 00c7 f87c shrl\.qb a2,a3,0x7 +0+00b0 <[^>]*> 0109 3b55 shrlv\.qb a3,t0,t1 +0+00b4 <[^>]*> 0109 0335 shra\.ph t0,t1,0x0 +0+00b8 <[^>]*> 0109 f335 shra\.ph t0,t1,0xf +0+00bc <[^>]*> 014b 498d shrav\.ph t1,t2,t3 +0+00c0 <[^>]*> 014b 0735 shra_r\.ph t2,t3,0x0 +0+00c4 <[^>]*> 014b f735 shra_r\.ph t2,t3,0xf +0+00c8 <[^>]*> 018d 5d8d shrav_r\.ph t3,t4,t5 +0+00cc <[^>]*> 018d 02f5 shra_r\.w t4,t5,0x0 +0+00d0 <[^>]*> 018d faf5 shra_r\.w t4,t5,0x1f +0+00d4 <[^>]*> 01cf 6ad5 shrav_r\.w t5,t6,t7 +0+00d8 <[^>]*> 020f 7095 muleu_s\.ph\.qbl t6,t7,s0 +0+00dc <[^>]*> 0230 78d5 muleu_s\.ph\.qbr t7,s0,s1 +0+00e0 <[^>]*> 0251 8115 mulq_rs\.ph s0,s1,s2 +0+00e4 <[^>]*> 0272 8825 muleq_s\.w\.phl s1,s2,s3 +0+00e8 <[^>]*> 0293 9065 muleq_s\.w\.phr s2,s3,s4 +0+00ec <[^>]*> 0293 20bc dpau\.h\.qbl \$ac0,s3,s4 +0+00f0 <[^>]*> 02b4 70bc dpau\.h\.qbr \$ac1,s4,s5 +0+00f4 <[^>]*> 02d5 a4bc dpsu\.h\.qbl \$ac2,s5,s6 +0+00f8 <[^>]*> 02f6 f4bc dpsu\.h\.qbr \$ac3,s6,s7 +0+00fc <[^>]*> 0317 02bc dpaq_s\.w\.ph \$ac0,s7,t8 +0+0100 <[^>]*> 0338 46bc dpsq_s\.w\.ph \$ac1,t8,t9 +0+0104 <[^>]*> 0359 bcbc mulsaq_s\.w\.ph \$ac2,t9,k0 +0+0108 <[^>]*> 037a d2bc dpaq_sa.l\.w \$ac3,k0,k1 +0+010c <[^>]*> 039b 16bc dpsq_sa.l\.w \$ac0,k1,gp +0+0110 <[^>]*> 03bc 5a7c maq_s\.w\.phl \$ac1,gp,sp +0+0114 <[^>]*> 03dd 8a7c maq_s\.w\.phr \$ac2,sp,s8 +0+0118 <[^>]*> 03fe fa7c maq_sa\.w\.phl \$ac3,s8,ra +0+011c <[^>]*> 001f 2a7c maq_sa\.w\.phr \$ac0,ra,zero +0+0120 <[^>]*> 0001 313c bitrev zero,at +0+0124 <[^>]*> 0022 413c insv at,v0 +0+0128 <[^>]*> 0040 05fc repl\.qb v0,0x0 +0+012c <[^>]*> 005f e5fc repl\.qb v0,0xff +0+0130 <[^>]*> 0064 133c replv\.qb v1,a0 +0+0134 <[^>]*> 0200 203d repl\.ph a0,-512 +0+0138 <[^>]*> 01ff 203d repl\.ph a0,511 +0+013c <[^>]*> 00a6 033c replv\.ph a1,a2 +0+0140 <[^>]*> 00e6 0245 cmpu\.eq\.qb a2,a3 +0+0144 <[^>]*> 0107 0285 cmpu\.lt\.qb a3,t0 +0+0148 <[^>]*> 0128 02c5 cmpu\.le\.qb t0,t1 +0+014c <[^>]*> 016a 48c5 cmpgu\.eq\.qb t1,t2,t3 +0+0150 <[^>]*> 018b 5105 cmpgu\.lt\.qb t2,t3,t4 +0+0154 <[^>]*> 01ac 5945 cmpgu\.le\.qb t3,t4,t5 +0+0158 <[^>]*> 01ac 0005 cmp\.eq\.ph t4,t5 +0+015c <[^>]*> 01cd 0045 cmp\.lt\.ph t5,t6 +0+0160 <[^>]*> 01ee 0085 cmp\.le\.ph t6,t7 +0+0164 <[^>]*> 0230 79ed pick\.qb t7,s0,s1 +0+0168 <[^>]*> 0251 822d pick\.ph s0,s1,s2 +0+016c <[^>]*> 0272 89ad packrl\.ph s1,s2,s3 +0+0170 <[^>]*> 0240 4e7c extr\.w s2,\$ac1,0x0 +0+0174 <[^>]*> 025f 4e7c extr\.w s2,\$ac1,0x1f +0+0178 <[^>]*> 0260 9e7c extr_r\.w s3,\$ac2,0x0 +0+017c <[^>]*> 027f 9e7c extr_r\.w s3,\$ac2,0x1f +0+0180 <[^>]*> 0280 ee7c extr_rs\.w s4,\$ac3,0x0 +0+0184 <[^>]*> 029f ee7c extr_rs\.w s4,\$ac3,0x1f +0+0188 <[^>]*> 02a0 3e7c extr_s\.h s5,\$ac0,0x0 +0+018c <[^>]*> 02bf 3e7c extr_s\.h s5,\$ac0,0x1f +0+0190 <[^>]*> 02d7 7ebc extrv_s\.h s6,\$ac1,s7 +0+0194 <[^>]*> 02f8 8ebc extrv\.w s7,\$ac2,t8 +0+0198 <[^>]*> 0319 debc extrv_r\.w t8,\$ac3,t9 +0+019c <[^>]*> 033a 2ebc extrv_rs\.w t9,\$ac0,k0 +0+01a0 <[^>]*> 0340 667c extp k0,\$ac1,0x0 +0+01a4 <[^>]*> 035f 667c extp k0,\$ac1,0x1f +0+01a8 <[^>]*> 037c a8bc extpv k1,\$ac2,gp +0+01ac <[^>]*> 0380 f67c extpdp gp,\$ac3,0x0 +0+01b0 <[^>]*> 039f f67c extpdp gp,\$ac3,0x1f +0+01b4 <[^>]*> 03be 38bc extpdpv sp,\$ac0,s8 +0+01b8 <[^>]*> 0020 401d shilo \$ac1,-32 +0+01bc <[^>]*> 001f 401d shilo \$ac1,31 +0+01c0 <[^>]*> 001e 927c shilov \$ac2,s8 +0+01c4 <[^>]*> 001f c27c mthlip ra,\$ac3 +0+01c8 <[^>]*> 0000 007c mfhi zero,\$ac0 +0+01cc <[^>]*> 0001 507c mflo at,\$ac1 +0+01d0 <[^>]*> 0002 a07c mthi v0,\$ac2 +0+01d4 <[^>]*> 0003 f07c mtlo v1,\$ac3 +0+01d8 <[^>]*> 0080 167c wrdsp a0,0x0 +0+01dc <[^>]*> 008f d67c wrdsp a0 +0+01e0 <[^>]*> 00af d67c wrdsp a1 +0+01e4 <[^>]*> 00c0 067c rddsp a2,0x0 +0+01e8 <[^>]*> 00cf c67c rddsp a2 +0+01ec <[^>]*> 00ef c67c rddsp a3 +0+01f0 <[^>]*> 012a 4225 lbux t0,t1\(t2\) +0+01f4 <[^>]*> 014b 4965 lhx t1,t2\(t3\) +0+01f8 <[^>]*> 016c 51a5 lwx t2,t3\(t4\) +0+01fc <[^>]*> 4360 fffe bposge32 000001fc + 1fc: R_MICROMIPS_PC16_S1 text_label +0+0200 <[^>]*> 0c00 nop +0+0202 <[^>]*> 018b 8abc madd \$ac2,t3,t4 +0+0206 <[^>]*> 01ac dabc maddu \$ac3,t4,t5 +0+020a <[^>]*> 01cd 2abc msub \$ac0,t5,t6 +0+020e <[^>]*> 01ee 7abc msubu \$ac1,t6,t7 +0+0212 <[^>]*> 02d5 ccbc mult \$ac3,s5,s6 +0+0216 <[^>]*> 02f6 1cbc multu \$ac0,s6,s7 +0+021a <[^>]*> 0c00 nop + \.\.\. diff --git a/gas/testsuite/gas/mips/micromips@mips32-dspr2.d b/gas/testsuite/gas/mips/micromips@mips32-dspr2.d new file mode 100644 index 00000000000..85c92cef918 --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@mips32-dspr2.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS DSP ASE Rev2 for MIPS32 +#as: -mdspr2 -32 +#source: mips32-dspr2.s + +# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly (microMIPS) + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 <[^>]*> 0001 013c absq_s\.qb zero,at +0+0004 <[^>]*> 0062 090d addu\.ph at,v0,v1 +0+0008 <[^>]*> 0083 150d addu_s\.ph v0,v1,a0 +0+000c <[^>]*> 00a4 194d adduh\.qb v1,a0,a1 +0+0010 <[^>]*> 00c5 254d adduh_r\.qb a0,a1,a2 +0+0014 <[^>]*> 00a6 0215 append a1,a2,0x0 +0+0018 <[^>]*> 00a6 fa15 append a1,a2,0x1f +0+001c <[^>]*> 0c00 nop +0+001e <[^>]*> 00c7 48bc balign a2,a3,0x1 +0+0022 <[^>]*> 00e6 31ad packrl\.ph a2,a2,a3 +0+0026 <[^>]*> 00c7 c8bc balign a2,a3,0x3 +0+002a <[^>]*> 0107 3185 cmpgdu\.eq\.qb a2,a3,t0 +0+002e <[^>]*> 0128 39c5 cmpgdu\.lt\.qb a3,t0,t1 +0+0032 <[^>]*> 0149 4205 cmpgdu\.le\.qb t0,t1,t2 +0+0036 <[^>]*> 0149 00bc dpa\.w\.ph \$ac0,t1,t2 +0+003a <[^>]*> 016a 44bc dps\.w\.ph \$ac1,t2,t3 +0+003e <[^>]*> 018b 8abc madd \$ac2,t3,t4 +0+0042 <[^>]*> 01ac dabc maddu \$ac3,t4,t5 +0+0046 <[^>]*> 01cd 2abc msub \$ac0,t5,t6 +0+004a <[^>]*> 01ee 7abc msubu \$ac1,t6,t7 +0+004e <[^>]*> 0230 782d mul\.ph t7,s0,s1 +0+0052 <[^>]*> 0251 842d mul_s\.ph s0,s1,s2 +0+0056 <[^>]*> 0272 8995 mulq_rs\.w s1,s2,s3 +0+005a <[^>]*> 0293 9155 mulq_s\.ph s2,s3,s4 +0+005e <[^>]*> 02b4 99d5 mulq_s\.w s3,s4,s5 +0+0062 <[^>]*> 02b4 acbc mulsa\.w\.ph \$ac2,s4,s5 +0+0066 <[^>]*> 02d5 ccbc mult \$ac3,s5,s6 +0+006a <[^>]*> 02f6 1cbc multu \$ac0,s6,s7 +0+006e <[^>]*> 0338 b86d precr\.qb\.ph s7,t8,t9 +0+0072 <[^>]*> 0319 03cd precr_sra\.ph\.w t8,t9,0x0 +0+0076 <[^>]*> 0319 fbcd precr_sra\.ph\.w t8,t9,0x1f +0+007a <[^>]*> 033a 07cd precr_sra_r\.ph\.w t9,k0,0x0 +0+007e <[^>]*> 033a ffcd precr_sra_r\.ph\.w t9,k0,0x1f +0+0082 <[^>]*> 035b 0255 prepend k0,k1,0x0 +0+0086 <[^>]*> 035b fa55 prepend k0,k1,0x1f +0+008a <[^>]*> 037c 01fc shra\.qb k1,gp,0x0 +0+008e <[^>]*> 037c e1fc shra\.qb k1,gp,0x7 +0+0092 <[^>]*> 039d 11fc shra_r\.qb gp,sp,0x0 +0+0096 <[^>]*> 039d f1fc shra_r\.qb gp,sp,0x7 +0+009a <[^>]*> 03df e9cd shrav\.qb sp,s8,ra +0+009e <[^>]*> 03e0 f5cd shrav_r\.qb s8,ra,zero +0+00a2 <[^>]*> 03e0 03fc shrl\.ph ra,zero,0x0 +0+00a6 <[^>]*> 03e0 f3fc shrl\.ph ra,zero,0xf +0+00aa <[^>]*> 0022 0315 shrlv\.ph zero,at,v0 +0+00ae <[^>]*> 0062 0b0d subu\.ph at,v0,v1 +0+00b2 <[^>]*> 0083 170d subu_s\.ph v0,v1,a0 +0+00b6 <[^>]*> 00a4 1b4d subuh\.qb v1,a0,a1 +0+00ba <[^>]*> 00c5 274d subuh_r\.qb a0,a1,a2 +0+00be <[^>]*> 00e6 284d addqh\.ph a1,a2,a3 +0+00c2 <[^>]*> 0107 344d addqh_r\.ph a2,a3,t0 +0+00c6 <[^>]*> 0128 388d addqh\.w a3,t0,t1 +0+00ca <[^>]*> 0149 448d addqh_r\.w t0,t1,t2 +0+00ce <[^>]*> 016a 4a4d subqh\.ph t1,t2,t3 +0+00d2 <[^>]*> 018b 564d subqh_r\.ph t2,t3,t4 +0+00d6 <[^>]*> 01ac 5a8d subqh\.w t3,t4,t5 +0+00da <[^>]*> 01cd 668d subqh_r\.w t4,t5,t6 +0+00de <[^>]*> 01cd 50bc dpax\.w\.ph \$ac1,t5,t6 +0+00e2 <[^>]*> 01ee 94bc dpsx\.w\.ph \$ac2,t6,t7 +0+00e6 <[^>]*> 020f e2bc dpaqx_s\.w\.ph \$ac3,t7,s0 +0+00ea <[^>]*> 0230 32bc dpaqx_sa\.w\.ph \$ac0,s0,s1 +0+00ee <[^>]*> 0251 66bc dpsqx_s\.w\.ph \$ac1,s1,s2 +0+00f2 <[^>]*> 0272 b6bc dpsqx_sa\.w\.ph \$ac2,s2,s3 +0+00f6 <[^>]*> 0c00 nop + \.\.\. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 92de0faabd1..b88782f077a 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1023,8 +1023,10 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test_arches "octeon2" [mips_arch_list_matching octeon2] run_dump_test "smartmips" - run_dump_test "mips32-dsp" - run_dump_test "mips32-dspr2" + run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32r2 \ + !octeon] + run_dump_test_arches "mips32-dspr2" [mips_arch_list_matching mips32r2 \ + !octeon] run_dump_test "mips64-dsp" run_dump_test "mips32-mt" diff --git a/gas/testsuite/gas/mips/mips32-dsp.d b/gas/testsuite/gas/mips/mips32-dsp.d index 0826972199e..b581b09f94a 100644 --- a/gas/testsuite/gas/mips/mips32-dsp.d +++ b/gas/testsuite/gas/mips/mips32-dsp.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses --show-raw-insn #name: MIPS DSP ASE for MIPS32 -#as: -mdsp -mips32r2 -32 +#as: -mdsp -32 # Check MIPS DSP ASE for MIPS32 Instruction Assembly diff --git a/gas/testsuite/gas/mips/mips32-dsp.s b/gas/testsuite/gas/mips/mips32-dsp.s index a39480c5903..6071fc5ac71 100644 --- a/gas/testsuite/gas/mips/mips32-dsp.s +++ b/gas/testsuite/gas/mips/mips32-dsp.s @@ -144,4 +144,5 @@ text_label: multu $ac0,$22,$23 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 .space 8 diff --git a/gas/testsuite/gas/mips/mips32-dspr2.d b/gas/testsuite/gas/mips/mips32-dspr2.d index 26f3a00ead2..90c20ef711c 100644 --- a/gas/testsuite/gas/mips/mips32-dspr2.d +++ b/gas/testsuite/gas/mips/mips32-dspr2.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses --show-raw-insn #name: MIPS DSP ASE Rev2 for MIPS32 -#as: -mdspr2 -mips32r2 -32 +#as: -mdspr2 -32 # Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly diff --git a/gas/testsuite/gas/mips/mips32-dspr2.s b/gas/testsuite/gas/mips/mips32-dspr2.s index e22d7980729..42cc2c98f4f 100644 --- a/gas/testsuite/gas/mips/mips32-dspr2.s +++ b/gas/testsuite/gas/mips/mips32-dspr2.s @@ -70,4 +70,5 @@ text_label: dpsqx_sa.w.ph $ac2,$18,$19 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 .space 8 diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 4b8d3002c1b..1091973b2b1 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,18 @@ +2012-07-31 Chao-Ying Fu + Catherine Moore + Maciej W. Rozycki + + * mips.h: Document microMIPS DSP ASE usage. + (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for + microMIPS DSP ASE support. + (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. + (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. + (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. + (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. + (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. + (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. + (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. + 2012-07-06 Maciej W. Rozycki * mips.h: Fix a typo in description. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 92325080be2..857fc7173de 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1494,6 +1494,24 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_MASK_IMMY 0x1ff #define MICROMIPSOP_SH_IMMY 1 +/* MIPS DSP ASE */ +#define MICROMIPSOP_MASK_DSPACC 0x3 +#define MICROMIPSOP_SH_DSPACC 14 +#define MICROMIPSOP_MASK_DSPSFT 0x3f +#define MICROMIPSOP_SH_DSPSFT 16 +#define MICROMIPSOP_MASK_SA3 0x7 +#define MICROMIPSOP_SH_SA3 13 +#define MICROMIPSOP_MASK_SA4 0xf +#define MICROMIPSOP_SH_SA4 12 +#define MICROMIPSOP_MASK_IMM8 0xff +#define MICROMIPSOP_SH_IMM8 13 +#define MICROMIPSOP_MASK_IMM10 0x3ff +#define MICROMIPSOP_SH_IMM10 16 +#define MICROMIPSOP_MASK_WRDSP 0x3f +#define MICROMIPSOP_SH_WRDSP 14 +#define MICROMIPSOP_MASK_BP 0x3 +#define MICROMIPSOP_SH_BP 14 + /* Placeholders for fields that only exist in the traditional 32-bit instruction encoding; see the comment above for details. */ #define MICROMIPSOP_MASK_CODE20 0 @@ -1508,28 +1526,12 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_SH_VECBYTE 0 #define MICROMIPSOP_MASK_VECALIGN 0 #define MICROMIPSOP_SH_VECALIGN 0 -#define MICROMIPSOP_MASK_DSPACC 0 -#define MICROMIPSOP_SH_DSPACC 0 #define MICROMIPSOP_MASK_DSPACC_S 0 #define MICROMIPSOP_SH_DSPACC_S 0 -#define MICROMIPSOP_MASK_DSPSFT 0 -#define MICROMIPSOP_SH_DSPSFT 0 #define MICROMIPSOP_MASK_DSPSFT_7 0 #define MICROMIPSOP_SH_DSPSFT_7 0 -#define MICROMIPSOP_MASK_SA3 0 -#define MICROMIPSOP_SH_SA3 0 -#define MICROMIPSOP_MASK_SA4 0 -#define MICROMIPSOP_SH_SA4 0 -#define MICROMIPSOP_MASK_IMM8 0 -#define MICROMIPSOP_SH_IMM8 0 -#define MICROMIPSOP_MASK_IMM10 0 -#define MICROMIPSOP_SH_IMM10 0 -#define MICROMIPSOP_MASK_WRDSP 0 -#define MICROMIPSOP_SH_WRDSP 0 #define MICROMIPSOP_MASK_RDDSP 0 #define MICROMIPSOP_SH_RDDSP 0 -#define MICROMIPSOP_MASK_BP 0 -#define MICROMIPSOP_SH_BP 0 #define MICROMIPSOP_MASK_MT_U 0 #define MICROMIPSOP_SH_MT_U 0 #define MICROMIPSOP_MASK_MT_H 0 @@ -1702,6 +1704,18 @@ extern const int bfd_mips16_num_opcodes; "f" 32-bit floating point constant "l" 32-bit floating point constant in .lit4 + DSP ASE usage: + "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) + "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) + "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) + "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) + "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) + "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) + "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) + "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) + "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) + "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) + Other: "()" parens surrounding optional value "," separates operands @@ -1709,8 +1723,8 @@ extern const int bfd_mips16_num_opcodes; "m" start of microMIPS extension sequence Characters used so far, for quick reference when adding more: - "1234567890" - "<>(),+.\|~" + "12345678 0" + "<>(),+.@\^|~" "ABCDEFGHI KLMN RST V " "abcd f hijklmnopqrstuvw yz" diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a1bd955ef77..32967e42ac6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2012-07-31 Chao-Ying Fu + Catherine Moore + Maciej W. Rozycki + + * micromips-opc.c (WR_a, RD_a, MOD_a): New macros. + (DSP_VOLA): Likewise. + (D32, D33): Likewise. + (micromips_opcodes): Add DSP ASE instructions. + * micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases. + <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise. + 2012-07-31 Jan Beulich * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2 diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index 0f18c714cd3..a15982dfd51 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -99,6 +99,14 @@ #define I1 INSN_ISA1 #define I3 INSN_ISA3 +/* MIPS DSP ASE support. */ +#define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */ +#define RD_a RD_HILO /* Read DSP accumulators (reuse RD_HILO). */ +#define MOD_a WR_a|RD_a +#define DSP_VOLA INSN_NO_DELAY_SLOT +#define D32 INSN_DSP +#define D33 INSN_DSPR2 + /* MIPS MCU (MicroController) ASE support. */ #define MC INSN_MCU @@ -650,10 +658,12 @@ const struct mips_opcode micromips_opcodes[] = {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, {"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, RD_b|RD_t|WR_d, 0, I1 }, {"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 }, +{"madd", "7,s,t", 0x00000abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, {"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 }, {"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 }, {"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 }, {"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 }, +{"maddu", "7,s,t", 0x00001abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, {"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_t|RD_C0, 0, I1 }, {"mfc0", "t,+D", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 }, {"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 }, @@ -665,8 +675,10 @@ const struct mips_opcode micromips_opcodes[] = {"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 }, {"mfhi", "mj", 0x4600, 0xffe0, RD_HI, WR_mj, I1 }, {"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_s|RD_HI, 0, I1 }, +{"mfhi", "s,7", 0x0000007c, 0xffe03fff, WR_s|RD_HI, 0, D32 }, {"mflo", "mj", 0x4640, 0xffe0, RD_LO, WR_mj, I1 }, {"mflo", "s", 0x00001d7c, 0xffe0ffff, WR_s|RD_LO, 0, I1 }, +{"mflo", "s,7", 0x0000107c, 0xffe03fff, WR_s|RD_LO, 0, D32 }, {"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 }, {"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 }, {"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 }, @@ -688,10 +700,12 @@ const struct mips_opcode micromips_opcodes[] = {"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S, 0, I1 }, {"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 }, {"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 }, +{"msub", "7,s,t", 0x00002abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, {"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 }, {"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 }, {"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 }, {"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 }, +{"msubu", "7,s,t", 0x00003abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, {"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I1 }, {"mtc0", "t,+D", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 }, {"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 }, @@ -702,7 +716,9 @@ const struct mips_opcode micromips_opcodes[] = {"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 }, {"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 }, {"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_s|WR_HI, 0, I1 }, +{"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_s|WR_HI, 0, D32 }, {"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_s|WR_LO, 0, I1 }, +{"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_s|WR_LO, 0, D32 }, {"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I1 }, {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, {"mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 }, @@ -713,7 +729,9 @@ const struct mips_opcode micromips_opcodes[] = {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, {"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"mult", "7,s,t", 0x00000cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, D32 }, {"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"multu", "7,s,t", 0x00001cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, D32 }, {"neg", "d,w", 0x00000190, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ {"negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ {"neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 }, @@ -965,6 +983,160 @@ const struct mips_opcode micromips_opcodes[] = {"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, {"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +/* MIPS DSP ASE. */ +{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"addq.ph", "d,s,t", 0x0000000d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addq_s.w", "d,s,t", 0x00000305, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addsc", "d,s,t", 0x00000385, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addu.qb", "d,s,t", 0x000000cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addwc", "d,s,t", 0x000003c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"bitrev", "t,s", 0x0000313c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"bposge32", "p", 0x43600000, 0xffff0000, CBD, 0, D32 }, +{"cmp.eq.ph", "s,t", 0x00000005, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmp.le.ph", "s,t", 0x00000085, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmp.lt.ph", "s,t", 0x00000045, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmpu.eq.qb", "s,t", 0x00000245, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpu.le.qb", "s,t", 0x000002c5, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpu.lt.qb", "s,t", 0x00000285, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsu.h.qbl", "7,s,t", 0x000024bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsu.h.qbr", "7,s,t", 0x000034bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"extpdp", "t,7,6", 0x0000367c, 0xfc003fff, WR_t|RD_a|DSP_VOLA, 0, D32 }, +{"extpdpv", "t,7,s", 0x000038bc, 0xfc003fff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, +{"extp", "t,7,6", 0x0000267c, 0xfc003fff, WR_t|RD_a, 0, D32 }, +{"extpv", "t,7,s", 0x000028bc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 }, +{"extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_t|RD_a, 0, D32 }, +{"extr_r.w", "t,7,6", 0x00001e7c, 0xfc003fff, WR_t|RD_a, 0, D32 }, +{"extr_s.h", "t,7,6", 0x00003e7c, 0xfc003fff, WR_t|RD_a, 0, D32 }, +{"extrv_rs.w", "t,7,s", 0x00002ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 }, +{"extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 }, +{"extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 }, +{"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 }, +{"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_t|RD_a, 0, D32 }, +{"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_d|RD_b|RD_t, 0, D32 }, +{"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_d|RD_b|RD_t, 0, D32 }, +{"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_d|RD_b|RD_t, 0, D32 }, +{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"modsub", "d,s,t", 0x00000295, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"mthlip", "s,7", 0x0000027c, 0xffe03fff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, +{"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"mulq_rs.ph", "d,s,t", 0x00000115, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 }, +{"packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"pick.ph", "d,s,t", 0x0000022d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"pick.qb", "d,s,t", 0x000001ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"preceq.w.phl", "t,s", 0x0000513c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"preceq.w.phr", "t,s", 0x0000613c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"preceu.ph.qbra", "t,s",0x0000d33c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"raddu.w.qb", "t,s", 0x0000f13c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"rddsp", "t", 0x000fc67c, 0xfc1fffff, WR_t, 0, D32 }, +{"rddsp", "t,8", 0x0000067c, 0xfc103fff, WR_t, 0, D32 }, +{"repl.ph", "d,@", 0x0000003d, 0xfc0007ff, WR_d, 0, D32 }, +{"repl.qb", "t,5", 0x000005fc, 0xfc001fff, WR_t, 0, D32 }, +{"replv.ph", "t,s", 0x0000033c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"replv.qb", "t,s", 0x0000133c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"shilo", "7,0", 0x0000001d, 0xffc03fff, MOD_a, 0, D32 }, +{"shilov", "7,s", 0x0000127c, 0xffe03fff, MOD_a|RD_s, 0, D32 }, +{"shll.ph", "t,s,4", 0x000003b5, 0xfc000fff, WR_t|RD_s, 0, D32 }, +{"shll.qb", "t,s,3", 0x0000087c, 0xfc001fff, WR_t|RD_s, 0, D32 }, +{"shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_t|RD_s, 0, D32 }, +{"shll_s.w", "t,s,^", 0x000003f5, 0xfc0007ff, WR_t|RD_s, 0, D32 }, +{"shllv.ph", "d,t,s", 0x0000038d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv.qb", "d,t,s", 0x00000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv_s.ph", "d,t,s", 0x0000078d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shra.ph", "t,s,4", 0x00000335, 0xfc000fff, WR_t|RD_s, 0, D32 }, +{"shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_t|RD_s, 0, D32 }, +{"shra_r.w", "t,s,^", 0x000002f5, 0xfc0007ff, WR_t|RD_s, 0, D32 }, +{"shrav.ph", "d,t,s", 0x0000018d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrav_r.ph", "d,t,s", 0x0000058d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrl.qb", "t,s,3", 0x0000187c, 0xfc001fff, WR_t|RD_s, 0, D32 }, +{"shrlv.qb", "d,t,s", 0x00000355, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq.ph", "d,s,t", 0x0000020d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq_s.w", "d,s,t", 0x00000345, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subu.qb", "d,s,t", 0x000002cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"wrdsp", "t", 0x000fd67c, 0xfc1fffff, RD_t|DSP_VOLA, 0, D32 }, +{"wrdsp", "t,8", 0x0000167c, 0xfc103fff, RD_t|DSP_VOLA, 0, D32 }, +/* MIPS DSP ASE Rev2. */ +{"absq_s.qb", "t,s", 0x0000013c, 0xfc00ffff, WR_t|RD_s, 0, D33 }, +{"addqh.ph", "d,s,t", 0x0000004d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh_r.ph", "d,s,t", 0x0000044d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh.w", "d,s,t", 0x0000008d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addu.ph", "d,s,t", 0x0000010d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh.qb", "d,s,t", 0x0000014d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh_r.qb", "d,s,t", 0x0000054d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"append", "t,s,h", 0x00000215, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, +{"balign", "t,s,2", 0x000008bc, 0xfc003fff, WR_t|RD_t|RD_s, 0, D33 }, +{"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"dpa.w.ph", "7,s,t", 0x000000bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dps.w.ph", "7,s,t", 0x000004bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 }, +{"mul.ph", "d,s,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mul_s.ph", "d,s,t", 0x0000042d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_s.w", "d,s,t", 0x000001d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulsa.w.ph", "7,s,t", 0x00002cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 }, +{"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"prepend", "t,s,h", 0x00000255, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"shra.qb", "t,s,3", 0x000001fc, 0xfc001fff, WR_t|RD_s, 0, D33 }, +{"shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_t|RD_s, 0, D33 }, +{"shrav.qb", "d,t,s", 0x000001cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrav_r.qb", "d,t,s", 0x000005cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrl.ph", "t,s,4", 0x000003fc, 0xfc000fff, WR_t|RD_s, 0, D33 }, +{"shrlv.ph", "d,t,s", 0x00000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu.ph", "d,s,t", 0x0000030d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh.qb", "d,s,t", 0x0000034d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh_r.qb", "d,s,t", 0x0000074d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh.ph", "d,s,t", 0x0000024d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, }; const int bfd_micromips_num_opcodes = diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 8990db85fb9..ace65a588c3 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -2411,6 +2411,39 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) infprintf (is, "0x%x", GET_OP (insn, STYPE)); break; + case '2': + infprintf (is, "0x%lx", GET_OP (insn, BP)); + break; + + case '3': + infprintf (is, "0x%lx", GET_OP (insn, SA3)); + break; + + case '4': + infprintf (is, "0x%lx", GET_OP (insn, SA4)); + break; + + case '5': + infprintf (is, "0x%lx", GET_OP (insn, IMM8)); + break; + + case '6': + infprintf (is, "0x%lx", GET_OP (insn, RS)); + break; + + case '7': + infprintf (is, "$ac%ld", GET_OP (insn, DSPACC)); + break; + + case '8': + infprintf (is, "0x%lx", GET_OP (insn, WRDSP)); + break; + + case '0': /* DSP 6-bit signed immediate in bit 16. */ + delta = (GET_OP (insn, DSPSFT) ^ 0x20) - 0x20; + infprintf (is, "%d", delta); + break; + case '<': infprintf (is, "0x%x", GET_OP (insn, SHAMT)); break; @@ -2419,6 +2452,10 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) infprintf (is, "0x%x", GET_OP (insn, 3BITPOS)); break; + case '^': + infprintf (is, "0x%lx", GET_OP (insn, RD)); + break; + case '|': infprintf (is, "0x%x", GET_OP (insn, TRAP)); break; @@ -2535,6 +2572,11 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) infprintf (is, "%s", mips_gpr_names[0]); break; + case '@': /* DSP 10-bit signed immediate in bit 16. */ + delta = (GET_OP (insn, IMM10) ^ 0x200) - 0x200; + infprintf (is, "%d", delta); + break; + case 'B': infprintf (is, "0x%x", GET_OP (insn, CODE10)); break; -- 2.30.2