From 04100de18d4e48420808556750cfcd7dadd05b8d Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Oct 2018 17:07:16 +0100
Subject: [PATCH] allow x2 (sp) to be redirected in C.LWSP

---
 riscv/insn_template_sv.cc |  6 ++++--
 riscv/sv_decode.h         | 25 +++++++++++++------------
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 9e27b80..cd63f07 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -30,6 +30,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   bool zeroingsrc = false;
 #endif
   sv_insn_t insn(p, bits, floatintmap, PRED_ARGS, OFFS_ARGS);
+  reg_t sp = 0;
   if (vlen > 0)
   {
     fprintf(stderr, "pre-ex reg %s %x %ld rd %ld rs1 %ld rs2 %ld vlen %d\n",
@@ -38,7 +39,8 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
             vlen);
 #ifdef INSN_CATEGORY_TWINPREDICATION
 #ifdef INSN_TYPE_C_STACK_LD
-    src_pred = insn.predicate(X_SP, SRC_PREDINT, zeroingsrc);
+    sp = insn._remap(X_SP, true, src_offs);
+    src_pred = insn.predicate(sp, SRC_PREDINT, zeroingsrc);
 #else
     src_pred = insn.predicate(s_insn.SRC_REG(), SRC_PREDINT, zeroingsrc);
 #endif
@@ -110,7 +112,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs), READ_REG(insn._rd()),
-                insn._rd(), insn.rvc_lwsp_imm(), READ_REG(X_SP));
+                insn._rd(), insn.rvc_lwsp_imm(), READ_REG(sp));
 #endif
       #include INCLUDEFILE
 #ifdef DEST_PREDINT
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 0bde06e..c74065f 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -62,6 +62,19 @@ public:
   bool stop_vloop(void);
 
   processor_t *p;
+
+  // cached version of remap: if remap is called multiple times
+  // by an emulated instruction it would increment the loop offset
+  // before it's supposed to.
+  uint64_t _remap(uint64_t reg, bool isint, int *offs)
+  {
+    if (sv_check_reg(isint, reg))
+    {
+        vloop_continue = true;
+    }
+    return remap(reg, isint, *offs);
+  }
+
 private:
   bool vloop_continue;
   unsigned int fimap;
@@ -79,18 +92,6 @@ private:
   // will need to take the current loop index/offset somehow
   uint64_t remap(uint64_t reg, bool isint, int offs);
 
-  // cached version of remap: if remap is called multiple times
-  // by an emulated instruction it would increment the loop offset
-  // before it's supposed to.
-  uint64_t _remap(uint64_t reg, bool isint, int *offs)
-  {
-    if (sv_check_reg(isint, reg))
-    {
-        vloop_continue = true;
-    }
-    return remap(reg, isint, *offs);
-  }
-
   uint64_t predicated(uint64_t reg, int offs, uint64_t pred);
 };
 
-- 
2.30.2