From 041477c4d3608c91f53834cbbe867db8763e9355 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 18 Mar 2022 12:41:04 +0000 Subject: [PATCH] move HyperRAMPads and Test PHY to hyperram.py module --- lambdasoc/periph/hyperram.py | 31 +++++++++++++++++++++++++++ lambdasoc/test/test_hyperbus.py | 38 +++++---------------------------- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py index 2fdf656..626043c 100644 --- a/lambdasoc/periph/hyperram.py +++ b/lambdasoc/periph/hyperram.py @@ -83,6 +83,37 @@ class HyperRAMASICPhy(Elaboratable): def ports(self): return list(self.io.fields.values()) + +# HyperRAM pads class (PHY) which can be used for testing and simulation +# (without needing a platform instance). use as: +# dut = HyperRAM(io=HyperRamPads(), phy_kls=TestHyperRAMPHY) + +class HyperRAMPads: + def __init__(self, dw=8): + self.clk = Signal() + self.cs_n = Signal() + self.dq = Record([("oe", 1), ("o", dw), ("i", dw)]) + self.rwds = Record([("oe", 1), ("o", dw//8), ("i", dw//8)]) + + +class TestHyperRAMPHY(Elaboratable): + def __init__(self, pads): + self.pads = pads + self.clk = pads.clk + self.cs = Signal() + self.dq_o = pads.dq.o + self.dq_i = pads.dq.i + self.dq_oe = pads.dq.oe + self.rwds_o = pads.rwds.o + self.rwds_oe = Signal() + + def elaborate(self, platform): + m = Module() + m.d.comb += self.pads.cs_n.eq(~self.cs) + m.d.comb += self.pads.rwds.oe.eq(self.rwds_oe) + return m + + # HyperRAM -------------------------------------------------------------------- class HyperRAM(Peripheral, Elaboratable): diff --git a/lambdasoc/test/test_hyperbus.py b/lambdasoc/test/test_hyperbus.py index 2191e63..3526bfc 100644 --- a/lambdasoc/test/test_hyperbus.py +++ b/lambdasoc/test/test_hyperbus.py @@ -2,6 +2,7 @@ # # Copyright (c) 2019 Florent Kermarrec # Copyright (c) 2021 Luke Kenneth Casson Leighton +# # Based on code from Kermarrec, Licensed BSD-2-Clause # # Modifications for the Libre-SOC Project funded by NLnet and NGI POINTER @@ -12,7 +13,7 @@ import unittest from nmigen import (Record, Module, Signal, Elaboratable) from nmigen.compat.sim import run_simulation -from lambdasoc.periph.hyperram import HyperRAM +from lambdasoc.periph.hyperram import HyperRAM, HyperRAMPads, TestHyperRAMPHY def c2bool(c): return {"-": 1, "_": 0}[c] @@ -46,35 +47,6 @@ def wb_read(bus, addr, sel): return (yield bus.dat_r) -class Pads: pass - - -class HyperRamPads: - def __init__(self, dw=8): - self.clk = Signal() - self.cs_n = Signal() - self.dq = Record([("oe", 1), ("o", dw), ("i", dw)]) - self.rwds = Record([("oe", 1), ("o", dw//8), ("i", dw//8)]) - - -class TestHyperRAMPHY(Elaboratable): - def __init__(self, pads): - self.pads = pads - self.clk = pads.clk - self.cs = Signal() - self.dq_o = pads.dq.o - self.dq_i = pads.dq.i - self.dq_oe = pads.dq.oe - self.rwds_o = pads.rwds.o - self.rwds_oe = Signal() - - def elaborate(self, platform): - m = Module() - m.d.comb += self.pads.cs_n.eq(~self.cs) - m.d.comb += self.pads.rwds.oe.eq(self.rwds_oe) - return m - - class TestHyperBusWrite(unittest.TestCase): def test_hyperram_write(self): @@ -123,7 +95,7 @@ class TestHyperBusWrite(unittest.TestCase): (yield dut.phy.pads.rwds.o)) yield - dut = HyperRAM(io=HyperRamPads(), phy_kls=TestHyperRAMPHY) + dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY) run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") @@ -161,7 +133,7 @@ class TestHyperBusWrite(unittest.TestCase): (yield dut.phy.pads.rwds.oe)) yield - dut = HyperRAM(io=HyperRamPads(), phy_kls=TestHyperRAMPHY) + dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY) run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="rd_sim.vcd") @@ -208,7 +180,7 @@ class TestHyperBusRead(unittest.TestCase): (yield dut.phy.pads.rwds.oe)) yield - dut = HyperRAM(io=HyperRamPads(), phy_kls=TestHyperRAMPHY) + dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY) run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="rd_sim.vcd") -- 2.30.2