From 0414bb63076676d6d64f134f35a96937ab31d77b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 19 May 2020 18:33:48 +0100 Subject: [PATCH] rename ALUPipeData to LogicalPipeData --- src/soc/fu/logical/main_stage.py | 2 +- src/soc/fu/logical/pipe_data.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index 41183b5b..17a57335 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -8,7 +8,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from nmutil.clz import CLZ -from soc.fu.logical.pipe_data import ALUInputData +from soc.fu.logical.pipe_data import LogicalInputData from soc.fu.alu.pipe_data import ALUOutputData from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import InternalOp diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index 65233fde..3b1b1351 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -3,7 +3,7 @@ from ieee754.fpcommon.getop import FPPipeContext from soc.fu.alu.pipe_data import IntegerData -class ALUInputData(IntegerData): +class LogicalInputData(IntegerData): def __init__(self, pspec): super().__init__(pspec) self.a = Signal(64, reset_less=True) # RA -- 2.30.2