From 0449fb2b7a51f911d9814b79250047fa8f083829 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 25 Jan 2009 20:31:17 -0800 Subject: [PATCH] X86: Fix a bug in the iret microcode. --- .../control_transfer/interrupts_and_exceptions.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 57bc13698..1f14eb95c 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py @@ -75,6 +75,8 @@ def macroop IRET_PROT { ld t2, ss, [1, t0, rsp], "1 * env.stackSize", dataSize=ssz ld t3, ss, [1, t0, rsp], "2 * env.stackSize", dataSize=ssz + # Read the handy m5 register for use later + rdm5reg t4 ### @@ -89,7 +91,6 @@ def macroop IRET_PROT { br label("protToVirtFallThrough"), flags=(nCECF,) #CPL=0 - rdm5reg t4 andi t0, t4, 0x30, flags=(EZF,) br label("protToVirtFallThrough"), flags=(nCEZF,) -- 2.30.2