From 048c6a9adcbe3dbf58cac405ebc39d94ea6c025b Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Fri, 26 Jan 2018 12:34:00 +0100 Subject: [PATCH] [ARC] Add support for reduced register file set gcc/ 2018-01-26 Claudiu Zissulescu * config/arc/arc-arches.def: Option mrf16 valid for all architectures. * config/arc/arc-c.def (__ARC_RF16__): New predefined macro. * config/arc/arc-cpus.def (em_mini): New cpu with rf16 on. * config/arc/arc-options.def (FL_RF16): Add mrf16 option. * config/arc/arc-tables.opt: Regenerate. * config/arc/arc.c (arc_conditional_register_usage): Handle reduced register file case. (arc_file_start): Set must have build attributes. * config/arc/arc.h (MAX_ARC_PARM_REGS): Conditional define using mrf16 option value. * config/arc/arc.opt (mrf16): Add new option. * config/arc/elf.h (ATTRIBUTE_PCS): Define. * config/arc/genmultilib.awk: Handle new mrf16 option. * config/arc/linux.h (ATTRIBUTE_PCS): Define. * config/arc/t-multilib: Regenerate. * doc/invoke.texi (ARC Options): Document mrf16 option. libgcc/ 2018-01-26 Claudiu Zissulescu * config/arc/lib1funcs.S (__udivmodsi4): Use safe version for RF16 option. (__divsi3): Use RF16 safe registers. (__modsi3): Likewise. From-SVN: r257083 --- gcc/ChangeLog | 20 ++++++++++++++++++++ gcc/config/arc/arc-arches.def | 8 ++++---- gcc/config/arc/arc-c.def | 1 + gcc/config/arc/arc-cpus.def | 1 + gcc/config/arc/arc-options.def | 2 +- gcc/config/arc/arc-tables.opt | 3 +++ gcc/config/arc/arc.c | 27 +++++++++++++++++++++++++++ gcc/config/arc/arc.h | 2 +- gcc/config/arc/arc.opt | 4 ++++ gcc/config/arc/elf.h | 4 ++++ gcc/config/arc/genmultilib.awk | 2 ++ gcc/config/arc/linux.h | 9 +++++++++ gcc/config/arc/t-multilib | 4 ++-- gcc/doc/invoke.texi | 12 +++++++++++- libgcc/ChangeLog | 7 +++++++ libgcc/config/arc/lib1funcs.S | 22 +++++++++++----------- 16 files changed, 108 insertions(+), 20 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8782ff8b17a..f4f61feaca0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2018-01-26 Claudiu Zissulescu + + * config/arc/arc-arches.def: Option mrf16 valid for all + architectures. + * config/arc/arc-c.def (__ARC_RF16__): New predefined macro. + * config/arc/arc-cpus.def (em_mini): New cpu with rf16 on. + * config/arc/arc-options.def (FL_RF16): Add mrf16 option. + * config/arc/arc-tables.opt: Regenerate. + * config/arc/arc.c (arc_conditional_register_usage): Handle + reduced register file case. + (arc_file_start): Set must have build attributes. + * config/arc/arc.h (MAX_ARC_PARM_REGS): Conditional define using + mrf16 option value. + * config/arc/arc.opt (mrf16): Add new option. + * config/arc/elf.h (ATTRIBUTE_PCS): Define. + * config/arc/genmultilib.awk: Handle new mrf16 option. + * config/arc/linux.h (ATTRIBUTE_PCS): Define. + * config/arc/t-multilib: Regenerate. + * doc/invoke.texi (ARC Options): Document mrf16 option. + 2018-01-26 Claudiu Zissulescu * config/arc/arc-protos.h: Add arc_is_secure_call_p proto. diff --git a/gcc/config/arc/arc-arches.def b/gcc/config/arc/arc-arches.def index 69e39447ed6..67dcb23c385 100644 --- a/gcc/config/arc/arc-arches.def +++ b/gcc/config/arc/arc-arches.def @@ -40,15 +40,15 @@ ARC_ARCH ("arcem", em, FL_MPYOPT_1_6 | FL_DIVREM | FL_CD | FL_NORM \ | FL_BS | FL_SWAP | FL_FPUS | FL_SPFP | FL_DPFP \ - | FL_SIMD | FL_FPUDA | FL_QUARK, 0) + | FL_SIMD | FL_FPUDA | FL_QUARK | FL_RF16, 0) ARC_ARCH ("archs", hs, FL_MPYOPT_7_9 | FL_DIVREM | FL_NORM | FL_CD \ | FL_ATOMIC | FL_LL64 | FL_BS | FL_SWAP \ - | FL_FPUS | FL_FPUD, \ + | FL_FPUS | FL_FPUD | FL_RF16, \ FL_CD | FL_ATOMIC | FL_BS | FL_NORM | FL_SWAP) ARC_ARCH ("arc6xx", 6xx, FL_BS | FL_NORM | FL_SWAP | FL_MUL64 | FL_MUL32x16 \ - | FL_SPFP | FL_ARGONAUT | FL_DPFP, 0) + | FL_SPFP | FL_ARGONAUT | FL_DPFP | FL_RF16, 0) ARC_ARCH ("arc700", 700, FL_ATOMIC | FL_BS | FL_NORM | FL_SWAP | FL_EA \ - | FL_SIMD | FL_SPFP | FL_ARGONAUT | FL_DPFP, \ + | FL_SIMD | FL_SPFP | FL_ARGONAUT | FL_DPFP | FL_RF16, \ FL_BS | FL_NORM | FL_SWAP) /* Local Variables: */ diff --git a/gcc/config/arc/arc-c.def b/gcc/config/arc/arc-c.def index aefaeb44313..04cce68fe8a 100644 --- a/gcc/config/arc/arc-c.def +++ b/gcc/config/arc/arc-c.def @@ -28,6 +28,7 @@ ARC_C_DEF ("__ARC_NORM__", TARGET_NORM) ARC_C_DEF ("__ARC_MUL64__", TARGET_MUL64_SET) ARC_C_DEF ("__ARC_MUL32BY16__", TARGET_MULMAC_32BY16_SET) ARC_C_DEF ("__ARC_SIMD__", TARGET_SIMD_SET) +ARC_C_DEF ("__ARC_RF16__", TARGET_RF16) ARC_C_DEF ("__ARC_UNALIGNED__", !STRICT_ALIGNMENT) ARC_C_DEF ("__ARC_BARREL_SHIFTER__", TARGET_BARREL_SHIFTER) diff --git a/gcc/config/arc/arc-cpus.def b/gcc/config/arc/arc-cpus.def index cedaefe6e6d..1fce81f6933 100644 --- a/gcc/config/arc/arc-cpus.def +++ b/gcc/config/arc/arc-cpus.def @@ -46,6 +46,7 @@ TUNE Tune value for the given configuration, otherwise NONE. */ ARC_CPU (em, em, 0, NONE) +ARC_CPU (em_mini, em, FL_RF16, NONE) ARC_CPU (arcem, em, FL_MPYOPT_2|FL_CD|FL_BS, NONE) ARC_CPU (em4, em, FL_CD, NONE) ARC_CPU (em4_dmips, em, FL_MPYOPT_2|FL_CD|FL_DIVREM|FL_NORM|FL_SWAP|FL_BS, NONE) diff --git a/gcc/config/arc/arc-options.def b/gcc/config/arc/arc-options.def index 31ddfb462f4..61ecd1de150 100644 --- a/gcc/config/arc/arc-options.def +++ b/gcc/config/arc/arc-options.def @@ -60,7 +60,7 @@ ARC_OPT (FL_CD, (1ULL << 0), MASK_CODE_DENSITY, "code density") ARC_OPT (FL_DIVREM, (1ULL << 1), MASK_DIVREM, "div/rem") ARC_OPT (FL_NORM, (1ULL << 2), MASK_NORM_SET, "norm") - +ARC_OPT (FL_RF16, (1ULL << 3), MASK_RF16, "rf16") ARC_OPT (FL_ATOMIC, (1ULL << 4), MASK_ATOMIC, "atomic") ARC_OPT (FL_LL64, (1ULL << 5), MASK_LL64, "double load/store") ARC_OPT (FL_BS, (1ULL << 6), MASK_BARREL_SHIFTER, "barrel shifter") diff --git a/gcc/config/arc/arc-tables.opt b/gcc/config/arc/arc-tables.opt index 56fa74b9f95..3b17b3de7d5 100644 --- a/gcc/config/arc/arc-tables.opt +++ b/gcc/config/arc/arc-tables.opt @@ -27,6 +27,9 @@ Known ARC CPUs (for use with the -mcpu= option): EnumValue Enum(processor_type) String(em) Value(PROCESSOR_em) +EnumValue +Enum(processor_type) String(em_mini) Value(PROCESSOR_em_mini) + EnumValue Enum(processor_type) String(arcem) Value(PROCESSOR_arcem) diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 1ad0bf601f6..fd10d0146a5 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1781,6 +1781,19 @@ arc_conditional_register_usage (void) reg_alloc_order [i] = i; } + /* Reduced configuration: don't use r4-r9, r16-r25. */ + if (TARGET_RF16) + { + for (i = 4; i <= 9; i++) + { + fixed_regs[i] = call_used_regs[i] = 1; + } + for (i = 16; i <= 25; i++) + { + fixed_regs[i] = call_used_regs[i] = 1; + } + } + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) if (!call_used_regs[regno]) CLEAR_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); @@ -5183,6 +5196,20 @@ static void arc_file_start (void) { default_file_start (); fprintf (asm_out_file, "\t.cpu %s\n", arc_cpu_string); + + /* Set some want to have build attributes. */ + asm_fprintf (asm_out_file, "\t.arc_attribute Tag_ARC_PCS_config, %d\n", + ATTRIBUTE_PCS); + asm_fprintf (asm_out_file, "\t.arc_attribute Tag_ARC_ABI_rf16, %d\n", + TARGET_RF16 ? 1 : 0); + asm_fprintf (asm_out_file, "\t.arc_attribute Tag_ARC_ABI_pic, %d\n", + flag_pic ? 2 : 0); + asm_fprintf (asm_out_file, "\t.arc_attribute Tag_ARC_ABI_tls, %d\n", + (arc_tp_regno != -1) ? 1 : 0); + asm_fprintf (asm_out_file, "\t.arc_attribute Tag_ARC_ABI_sda, %d\n", + TARGET_NO_SDATA_SET ? 0 : 2); + asm_fprintf (asm_out_file, "\t.arc_attribute Tag_ARC_ABI_exceptions, %d\n", + TARGET_OPTFPE ? 1 : 0); } /* Implement `TARGET_ASM_FILE_END'. */ diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index 02a4b64c70f..38021123c0d 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -727,7 +727,7 @@ arc_return_addr_rtx(COUNT,FRAME) ((CUM) = 0) /* The number of registers used for parameter passing. Local to this file. */ -#define MAX_ARC_PARM_REGS 8 +#define MAX_ARC_PARM_REGS (TARGET_RF16 ? 4 : 8) /* 1 if N is a possible register number for function argument passing. */ #define FUNCTION_ARG_REGNO_P(N) \ diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index 5f10c0ee005..bc11ca1ffe6 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -523,3 +523,7 @@ Enum(arc_lpc) String(28) Value(28) EnumValue Enum(arc_lpc) String(32) Value(32) + +mrf16 +Target Report Mask(RF16) +Enable 16-entry register file. diff --git a/gcc/config/arc/elf.h b/gcc/config/arc/elf.h index 3bb9cb012ae..43ced3b720f 100644 --- a/gcc/config/arc/elf.h +++ b/gcc/config/arc/elf.h @@ -67,5 +67,9 @@ along with GCC; see the file COPYING3. If not see #undef TARGET_AUTO_MODIFY_REG_DEFAULT #define TARGET_AUTO_MODIFY_REG_DEFAULT 1 +/* Build attribute: procedure call standard. */ +#undef ATTRIBUTE_PCS +#define ATTRIBUTE_PCS 2 + #undef TARGET_ASM_FILE_END #define TARGET_ASM_FILE_END arc_file_end diff --git a/gcc/config/arc/genmultilib.awk b/gcc/config/arc/genmultilib.awk index 9cfbd12fda4..785007e7efa 100644 --- a/gcc/config/arc/genmultilib.awk +++ b/gcc/config/arc/genmultilib.awk @@ -130,6 +130,8 @@ BEGIN { line = line "/spfp" else if (cpu_flg[i] == "FL_DPFP") line = line "/dpfp" + else if (cpu_flg[i] == "FL_RF16") + line = line "/mrf16" else { print "Don't know the flag " cpu_flg[i] > "/dev/stderr" diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h index 385083331d5..4e87dfe3ac1 100644 --- a/gcc/config/arc/linux.h +++ b/gcc/config/arc/linux.h @@ -100,3 +100,12 @@ along with GCC; see the file COPYING3. If not see #undef LINK_EH_SPEC #define LINK_EH_SPEC "--eh-frame-hdr" #endif + +#undef SUBTARGET_CPP_SPEC +#define SUBTARGET_CPP_SPEC "\ + %{pthread:-D_REENTRANT} \ +" + +/* Build attribute: procedure call standard. */ +#undef ATTRIBUTE_PCS +#define ATTRIBUTE_PCS 3 diff --git a/gcc/config/arc/t-multilib b/gcc/config/arc/t-multilib index a7a2cadc146..d9ab0ca1da3 100644 --- a/gcc/config/arc/t-multilib +++ b/gcc/config/arc/t-multilib @@ -21,9 +21,9 @@ # along with GCC; see the file COPYING3. If not see # . -MULTILIB_OPTIONS = mcpu=em/mcpu=arcem/mcpu=em4/mcpu=em4_dmips/mcpu=em4_fpus/mcpu=em4_fpuda/mcpu=quarkse_em/mcpu=hs/mcpu=archs/mcpu=hs34/mcpu=hs38/mcpu=hs38_linux/mcpu=arc600/mcpu=arc600_norm/mcpu=arc600_mul64/mcpu=arc600_mul32x16/mcpu=arc601/mcpu=arc601_norm/mcpu=arc601_mul64/mcpu=arc601_mul32x16/mcpu=arc700/mcpu=nps400 +MULTILIB_OPTIONS = mcpu=em/mcpu=em_mini/mcpu=arcem/mcpu=em4/mcpu=em4_dmips/mcpu=em4_fpus/mcpu=em4_fpuda/mcpu=quarkse_em/mcpu=hs/mcpu=archs/mcpu=hs34/mcpu=hs38/mcpu=hs38_linux/mcpu=hs4x/mcpu=hs4xd/mcpu=arc600/mcpu=arc600_norm/mcpu=arc600_mul64/mcpu=arc600_mul32x16/mcpu=arc601/mcpu=arc601_norm/mcpu=arc601_mul64/mcpu=arc601_mul32x16/mcpu=arc700/mcpu=nps400 -MULTILIB_DIRNAMES = em arcem em4 em4_dmips em4_fpus em4_fpuda quarkse_em hs archs hs34 hs38 hs38_linux arc600 arc600_norm arc600_mul64 arc600_mul32x16 arc601 arc601_norm arc601_mul64 arc601_mul32x16 arc700 nps400 +MULTILIB_DIRNAMES = em em_mini arcem em4 em4_dmips em4_fpus em4_fpuda quarkse_em hs archs hs34 hs38 hs38_linux hs4x hs4xd arc600 arc600_norm arc600_mul64 arc600_mul32x16 arc601 arc601_norm arc601_mul64 arc601_mul32x16 arc700 nps400 # Aliases: MULTILIB_MATCHES = mcpu?arc600=mcpu?ARC600 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 328ee849b0b..c07dd062490 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -628,7 +628,7 @@ Objective-C and Objective-C++ Dialects}. -mmixed-code -mq-class -mRcq -mRcw -msize-level=@var{level} @gol -mtune=@var{cpu} -mmultcost=@var{num} @gol -munalign-prob-threshold=@var{probability} -mmpy-option=@var{multo} @gol --mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu}} +-mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16} @emph{ARM Options} @gccoptlist{-mapcs-frame -mno-apcs-frame @gol @@ -14963,6 +14963,10 @@ instructions enabled. @item nps400 Compile for ARC 700 on NPS400 chip. +@item em_mini +Compile for ARC EM minimalist configuration featuring reduced register +set. + @end table @item -mdpfp @@ -15221,6 +15225,12 @@ specified, the compiler and run-time library might continue to use the loop mechanism for various needs. This option defines macro @code{__ARC_LPC_WIDTH__} with the value of @var{width}. +@item -mrf16 +@opindex mrf16 +This option instructs the compiler to generate code for a 16-entry +register file. This option defines the @code{__ARC_RF16__} +preprocessor macro. + @end table The following options are passed through to the assembler, and also diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 778a455ca71..79c79e8c31c 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,10 @@ +2018-01-26 Claudiu Zissulescu + + * config/arc/lib1funcs.S (__udivmodsi4): Use safe version for RF16 + option. + (__divsi3): Use RF16 safe registers. + (__modsi3): Likewise. + 2018-01-23 Max Filippov * config/xtensa/ieee754-df.S (__addsf3, __subsf3, __mulsf3) diff --git a/libgcc/config/arc/lib1funcs.S b/libgcc/config/arc/lib1funcs.S index f70cfd2f7f7..9a626022612 100644 --- a/libgcc/config/arc/lib1funcs.S +++ b/libgcc/config/arc/lib1funcs.S @@ -370,7 +370,7 @@ SYM(__udivmodsi4): mov_s r0,1 j_s.d [blink] mov.c r0,0 -#elif !defined (__OPTIMIZE_SIZE__) +#elif !defined (__OPTIMIZE_SIZE__) && !defined (__ARC_RF16__) #if defined (__ARC_NORM__) && defined (__ARC_BARREL_SHIFTER__) lsr_s r2,r0 brhs.d r1,r2,.Lret0_3 @@ -509,14 +509,14 @@ SYM(__udivsi3): #ifndef __ARC_EA__ SYM(__divsi3): /* A5 / ARC60? */ - mov r7,blink - xor r6,r0,r1 + mov r12,blink + xor r11,r0,r1 abs_s r0,r0 bl.d @SYM(__udivmodsi4) - abs_s r1,r1 - tst r6,r6 - j.d [r7] - neg.mi r0,r0 + abs_s r1,r1 + tst r11,r11 + j.d [r12] + neg.mi r0,r0 #else /* !ifndef __ARC_EA__ */ ;; We can use the abs, norm, divaw and mpy instructions for ARC700 #define MULDIV @@ -913,14 +913,14 @@ SYM(__modsi3): #ifndef __ARC_EA__ /* A5 / ARC60? */ mov_s r12,blink - mov_s r6,r0 + mov_s r11,r0 abs_s r0,r0 bl.d @SYM(__udivmodsi4) - abs_s r1,r1 - tst r6,r6 + abs_s r1,r1 + tst r11,r11 neg_s r0,r1 j_s.d [r12] - mov.pl r0,r1 + mov.pl r0,r1 #else /* __ARC_EA__ */ abs_s r2,r1 norm.f r4,r0 -- 2.30.2