From 0498a2be0d546594c9225f7ba6dc080722a79ecb Mon Sep 17 00:00:00 2001 From: Ramana Radhakrishnan Date: Tue, 28 Jun 2011 14:54:58 +0000 Subject: [PATCH] Fix constraints. 2011-06-28 Ramana Radhakrishnan * config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier with '=' constraint modifier. (*divdf3_vfp): Likewise. ("*mulsf3_vfp"): Likewise. ("*muldf3_vfp"): Likewise. ("*mulsf3negsf_vfp"): Likewise. ("*muldf3negdf_vfp"): Likewise. From-SVN: r175588 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/arm/vfp.md | 13 ++++++------- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1ce67633953..23997c43a41 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2011-06-28 Ramana Radhakrishnan + + * config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier + with '=' constraint modifier. + (*divdf3_vfp): Likewise. + ("*mulsf3_vfp"): Likewise. + ("*muldf3_vfp"): Likewise. + ("*mulsf3negsf_vfp"): Likewise. + ("*muldf3negdf_vfp"): Likewise. + 2011-06-28 Nick Clifton * config/mn10300/mn10300.h (LINK_SPEC): Do not use linker diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 42be2ff3acc..e2165a8cfe3 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -719,7 +719,7 @@ ;; Division insns (define_insn "*divsf3_vfp" - [(set (match_operand:SF 0 "s_register_operand" "+t") + [(set (match_operand:SF 0 "s_register_operand" "=t") (div:SF (match_operand:SF 1 "s_register_operand" "t") (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" @@ -729,7 +729,7 @@ ) (define_insn "*divdf3_vfp" - [(set (match_operand:DF 0 "s_register_operand" "+w") + [(set (match_operand:DF 0 "s_register_operand" "=w") (div:DF (match_operand:DF 1 "s_register_operand" "w") (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" @@ -742,7 +742,7 @@ ;; Multiplication insns (define_insn "*mulsf3_vfp" - [(set (match_operand:SF 0 "s_register_operand" "+t") + [(set (match_operand:SF 0 "s_register_operand" "=t") (mult:SF (match_operand:SF 1 "s_register_operand" "t") (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" @@ -752,7 +752,7 @@ ) (define_insn "*muldf3_vfp" - [(set (match_operand:DF 0 "s_register_operand" "+w") + [(set (match_operand:DF 0 "s_register_operand" "=w") (mult:DF (match_operand:DF 1 "s_register_operand" "w") (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" @@ -761,9 +761,8 @@ (set_attr "type" "fmuld")] ) - (define_insn "*mulsf3negsf_vfp" - [(set (match_operand:SF 0 "s_register_operand" "+t") + [(set (match_operand:SF 0 "s_register_operand" "=t") (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t")) (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" @@ -773,7 +772,7 @@ ) (define_insn "*muldf3negdf_vfp" - [(set (match_operand:DF 0 "s_register_operand" "+w") + [(set (match_operand:DF 0 "s_register_operand" "=w") (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" -- 2.30.2