From 04999f4af0f6e5c46843d9212abb0c962f533cca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 1 Mar 2014 17:47:19 +0100 Subject: [PATCH] Fixed vhdl2verilog help message --- frontends/vhdl2verilog/vhdl2verilog.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index 9e9953ced..367e63fe0 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -35,9 +35,8 @@ struct Vhdl2verilogPass : public Pass { log("\n"); log(" vhdl2verilog [options] ..\n"); log("\n"); - log("This pass looks for subcircuits that are isomorphic to any of the modules\n"); - log("in the given map file and replaces them with instances of this modules. The\n"); - log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n"); + log("This command reads VHDL source files using the 'vhdl2verilog' tool and the\n"); + log("Yosys Verilog frontend.\n"); log("\n"); log(" -out \n"); log(" do not import the vhdl2verilog output. instead write it to the\n"); -- 2.30.2