From 04a2859e888f8489e15f9d2c920edc773b761d81 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 26 Jul 2020 12:13:36 +0100 Subject: [PATCH] convert LDST test to accumulator style --- src/soc/fu/compunits/test/test_compunit.py | 5 +- .../fu/compunits/test/test_ldst_compunit.py | 2 +- src/soc/fu/ldst/test/test_pipe_caller.py | 48 +++++++------------ src/soc/fu/test/common.py | 6 ++- 4 files changed, 26 insertions(+), 35 deletions(-) diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 20c58e11..62ad9ec2 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -171,7 +171,7 @@ class TestRunner(FHDLTestCase): self.funit = funit self.bigendian = bigendian - def execute(self, cu, instruction, pdecode2, simdec2, test): + def execute(self, cu, l0, instruction, pdecode2, simdec2, test): program = test.program print("test", test.name, test.mem) @@ -329,6 +329,7 @@ class TestRunner(FHDLTestCase): m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel else: m.submodules.cu = cu = self.fukls(0) + l0 = None comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) @@ -342,7 +343,7 @@ class TestRunner(FHDLTestCase): for test in self.test_data: print(test.name) with self.subTest(test.name): - yield from self.execute(cu, instruction, + yield from self.execute(cu, l0, instruction, pdecode2, simdec2, test) diff --git a/src/soc/fu/compunits/test/test_ldst_compunit.py b/src/soc/fu/compunits/test/test_ldst_compunit.py index 0f9211f2..a5fff3c2 100644 --- a/src/soc/fu/compunits/test/test_ldst_compunit.py +++ b/src/soc/fu/compunits/test/test_ldst_compunit.py @@ -59,7 +59,7 @@ class LDSTTestRunner(TestRunner): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - suite.addTest(LDSTTestRunner(LDSTTestCase.test_data)) + suite.addTest(LDSTTestRunner(LDSTTestCase().test_data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py index 9e601e3e..31ddfc52 100644 --- a/src/soc/fu/ldst/test/test_pipe_caller.py +++ b/src/soc/fu/ldst/test/test_pipe_caller.py @@ -1,6 +1,5 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import special_sprs @@ -13,7 +12,7 @@ from soc.decoder.isa.all import ISA from soc.config.endian import bigendian -from soc.fu.test.common import TestCase +from soc.fu.test.common import TestAccumulatorBase, TestCase from soc.fu.ldst.pipe_data import LDSTPipeSpec import random @@ -50,20 +49,9 @@ def get_cu_inputs(dec2, sim): return res -class LDSTTestCase(FHDLTestCase): - test_data = [] +class LDSTTestCase(TestAccumulatorBase): - def __init__(self, name): - super().__init__(name) - self.test_name = name - - def run_tst_program(self, prog, initial_regs=None, - initial_sprs=None, initial_mem=None): - tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, - mem=initial_mem) - self.test_data.append(tc) - - def test_1_load(self): + def case_1_load(self): lst = ["lhz 3, 0(1)"] initial_regs = [0] * 32 initial_regs[1] = 0x0004 @@ -72,10 +60,10 @@ class LDSTTestCase(FHDLTestCase): 0x0008: (0xabcdef0187654321, 8), 0x0020: (0x1828384822324252, 8), } - self.run_tst_program(Program(lst, bigendian), initial_regs, + self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) - def test_2_load_store(self): + def case_2_load_store(self): lst = [ "stb 3, 1(2)", "lbz 4, 1(2)", @@ -88,10 +76,10 @@ class LDSTTestCase(FHDLTestCase): 0x0008: (0xabcdef0187654321, 8), 0x0020: (0x1828384822324252, 8), } - self.run_tst_program(Program(lst, bigendian), initial_regs, + self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) - def test_3_load_store(self): + def case_3_load_store(self): lst = ["sth 4, 0(2)", "lhz 4, 0(2)"] initial_regs = [0] * 32 @@ -102,10 +90,10 @@ class LDSTTestCase(FHDLTestCase): 0x0008: (0xabcdef0187654321, 8), 0x0020: (0x1828384822324252, 8), } - self.run_tst_program(Program(lst, bigendian), initial_regs, + self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) - def test_4_load_store_rev_ext(self): + def case_4_load_store_rev_ext(self): lst = ["stwx 1, 4, 2", "lwbrx 3, 4, 2"] initial_regs = [0] * 32 @@ -116,10 +104,10 @@ class LDSTTestCase(FHDLTestCase): 0x0008: (0xabcdef0187654321, 8), 0x0020: (0x1828384822324252, 8), } - self.run_tst_program(Program(lst, bigendian), initial_regs, + self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) - def test_5_load_store_rev_ext(self): + def case_5_load_store_rev_ext(self): lst = ["stwbrx 1, 4, 2", "lwzx 3, 4, 2"] initial_regs = [0] * 32 @@ -130,10 +118,10 @@ class LDSTTestCase(FHDLTestCase): 0x0008: (0xabcdef0187654321, 8), 0x0020: (0x1828384822324252, 8), } - self.run_tst_program(Program(lst, bigendian), initial_regs, + self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) - def test_6_load_store_rev_ext(self): + def case_6_load_store_rev_ext(self): lst = ["stwbrx 1, 4, 2", "lwbrx 3, 4, 2"] initial_regs = [0] * 32 @@ -144,10 +132,10 @@ class LDSTTestCase(FHDLTestCase): 0x0008: (0xabcdef0187654321, 8), 0x0020: (0x1828384822324252, 8), } - self.run_tst_program(Program(lst, bigendian), initial_regs, + self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) - def test_7_load_store_d(self): + def case_7_load_store_d(self): lst = [ "std 3, 0(2)", "ld 4, 0(2)", @@ -160,10 +148,10 @@ class LDSTTestCase(FHDLTestCase): 0x0008: (0xabcdef0187654321, 8), 0x0020: (0x1828384822324252, 8), } - self.run_tst_program(Program(lst, bigendian), initial_regs, + self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) - def test_8_load_store_d_update(self): + def case_8_load_store_d_update(self): lst = [ "stdu 3, 0(2)", "ld 4, 0(2)", @@ -176,6 +164,6 @@ class LDSTTestCase(FHDLTestCase): 0x0008: (0xabcdef0187654321, 8), 0x0020: (0x1828384822324252, 8), } - self.run_tst_program(Program(lst, bigendian), initial_regs, + self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index 2cfd6ce2..6d6181d7 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -20,12 +20,14 @@ class TestAccumulatorBase: v(self) def add_case(self, prog, initial_regs=None, initial_sprs=None, - initial_cr=0, initial_msr=0): + initial_cr=0, initial_msr=0, + initial_mem=None): test_name = inspect.stack()[1][3] # name of caller of this function tc = TestCase(prog, test_name, regs=initial_regs, sprs=initial_sprs, cr=initial_cr, - msr=initial_msr) + msr=initial_msr, + mem=initial_mem) self.test_data.append(tc) -- 2.30.2