From 04aad087e4493a4d39cca928c8d2f3a1461b1736 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 7 Sep 2020 17:13:09 +0100 Subject: [PATCH] convert CR to PowerDecodeSubset format --- src/soc/decoder/isa/caller.py | 34 ++++++++++++++++++++------ src/soc/fu/cr/test/test_pipe_caller.py | 14 ++++++----- src/soc/fu/test/common.py | 6 +++-- 3 files changed, 38 insertions(+), 16 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 293c81c6..b4c7f1fe 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -567,10 +567,18 @@ class ISACaller: int_op = yield self.dec2.dec.op.internal_op # sigh reconstruct the assembly instruction name - ov_en = yield self.dec2.e.do.oe.oe - ov_ok = yield self.dec2.e.do.oe.ok - rc_en = yield self.dec2.e.do.rc.rc - rc_ok = yield self.dec2.e.do.rc.ok + if hasattr(self.dec2.e.do, "oe"): + ov_en = yield self.dec2.e.do.oe.oe + ov_ok = yield self.dec2.e.do.oe.ok + else: + ov_en = False + ov_ok = False + if hasattr(self.dec2.e.do, "rc"): + rc_en = yield self.dec2.e.do.rc.rc + rc_ok = yield self.dec2.e.do.rc.ok + else: + rc_en = False + rc_ok = False # grrrr have to special-case MUL op (see DecodeOE) print("ov %d en %d rc %d en %d op %d" % \ (ov_ok, ov_en, rc_ok, rc_en, int_op)) @@ -715,7 +723,10 @@ class ISACaller: already_done |= 2 print("carry already done?", bin(already_done)) - carry_en = yield self.dec2.e.do.output_carry + if hasattr(self.dec2.e.do, "outout_carry"): + carry_en = yield self.dec2.e.do.output_carry + else: + carry_en = False if carry_en: yield from self.handle_carry_(inputs, results, already_done) @@ -726,13 +737,20 @@ class ISACaller: if name == 'overflow': overflow = output - ov_en = yield self.dec2.e.do.oe.oe - ov_ok = yield self.dec2.e.do.oe.ok + if hasattr(self.dec2.e.do, "oe"): + ov_en = yield self.dec2.e.do.oe.oe + ov_ok = yield self.dec2.e.do.oe.ok + else: + ov_en = False + ov_ok = False print("internal overflow", overflow, ov_en, ov_ok) if ov_en & ov_ok: yield from self.handle_overflow(inputs, results, overflow) - rc_en = yield self.dec2.e.do.rc.rc + if hasattr(self.dec2.e.do, "rc"): + rc_en = yield self.dec2.e.do.rc.rc + else: + rc_en = False if rc_en: self.handle_comparison(results) diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 8b8a4616..82dac148 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -237,8 +237,8 @@ def get_cu_inputs(dec2, sim): """naming (res) must conform to CRFunctionUnit input regspec """ res = {} - full_reg = yield dec2.e.do.read_cr_whole.data - full_reg_ok = yield dec2.e.do.read_cr_whole.ok + full_reg = yield dec2.dec_cr_in.whole_reg.data + full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok full_cr_mask = mask_extend(full_reg, 8, 4) # full CR @@ -272,8 +272,8 @@ class TestRunner(unittest.TestCase): yield from ALUHelpers.set_int_rb(alu, dec2, inp) def assert_outputs(self, alu, dec2, simulator, code): - whole_reg_ok = yield dec2.e.do.write_cr_whole.ok - whole_reg_data = yield dec2.e.do.write_cr_whole.data + whole_reg_ok = yield dec2.dec_cr_out.whole_reg.ok + whole_reg_data = yield dec2.dec_cr_out.whole_reg.data full_cr_mask = mask_extend(whole_reg_data, 8, 4) cr_en = yield dec2.e.write_cr.ok @@ -340,9 +340,11 @@ class TestRunner(unittest.TestCase): comb = m.d.comb instruction = Signal(32) - pdecode = create_pdecode() + fn_name = "CR" + opkls = CRPipeSpec.opsubsetkls - m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) + m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) + pdecode = pdecode2.dec pspec = CRPipeSpec(id_wid=2) m.submodules.alu = alu = CRBasePipe(pspec) diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index 6e1e59a9..6489f5a0 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -232,6 +232,8 @@ class ALUHelpers: yield alu.p.data_i.rb.eq(0) if 'rb' in inp: yield alu.p.data_i.rb.eq(inp['rb']) + if not hasattr(dec2.e.do, "imm_data"): + return # If there's an immediate, set the B operand to that imm_ok = yield dec2.e.do.imm_data.ok if imm_ok: @@ -300,8 +302,8 @@ class ALUHelpers: def set_full_cr(alu, dec2, inp): if 'full_cr' in inp: - full_reg = yield dec2.e.do.read_cr_whole.data - full_reg_ok = yield dec2.e.do.read_cr_whole.ok + full_reg = yield dec2.dec_cr_in.whole_reg.data + full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok full_cr_mask = mask_extend(full_reg, 8, 4) yield alu.p.data_i.full_cr.eq(inp['full_cr'] & full_cr_mask) else: -- 2.30.2