From 04ad0b08e5024558f23069ce482e2cbc60b2ae9e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 30 Apr 2021 14:09:17 +0100 Subject: [PATCH] add basic test_issuer_mmu.py for running specifically with microwatt_mmu=True --- src/soc/simple/test/test_issuer_mmu.py | 45 ++++++++++++++++++++++++++ src/soc/simple/test/test_runner.py | 5 ++- 2 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 src/soc/simple/test/test_issuer_mmu.py diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py new file mode 100644 index 00000000..13b278b2 --- /dev/null +++ b/src/soc/simple/test/test_issuer_mmu.py @@ -0,0 +1,45 @@ +"""simple core test, runs instructions from a TestMemory + +related bugs: + + * https://bugs.libre-soc.org/show_bug.cgi?id=363 +""" + +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git + +import unittest +import sys + +# here is the logic which takes test cases and "executes" them. +# in this instance (TestRunner) its job is to instantiate both +# a Libre-SOC nmigen-based HDL instance and an ISACaller python +# simulator. it's also responsible for performing the single +# step and comparison. +from soc.simple.test.test_runner import TestRunner + +# test with MMU +from openpower.test.mmu.mmu_cases import MMUTestCase +#from openpower.test.ldst.ldst_cases import LDSTTestCase +#from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase) + +if __name__ == "__main__": + svp64 = True + if len(sys.argv) == 2: + if sys.argv[1] == 'nosvp64': + svp64 = False + sys.argv.pop() + + print ("SVP64 test mode enabled", svp64) + + unittest.main(exit=False) + suite = unittest.TestSuite() + #suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64, + # microwatt_mmu=True)) + #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64, + # microwatt_mmu=True)) + suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64, + microwatt_mmu=True)) + + runner = unittest.TextTestRunner() + runner.run(suite) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 108c9c77..e111d8b4 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -135,7 +135,10 @@ class TestRunner(FHDLTestCase): pc_i = Signal(32) svstate_i = Signal(32) - ldst_ifacetype = 'mmu_cache_wb' if microwatt_mmu else 'test_bare_wb' + if self.microwatt_mmu: + ldst_ifacetype = 'mmu_cache_wb' + else: + ldst_ifacetype = 'test_bare_wb' imem_ifacetype = 'test_bare_wb' pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype, -- 2.30.2