From 04b72e35379c2847b5f0ad190000515774fa7adb Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 26 Aug 2024 00:31:46 +0100 Subject: [PATCH] --- crypto_router_asic.mdwn | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn index ce1381ac1..c98e3e0da 100644 --- a/crypto_router_asic.mdwn +++ b/crypto_router_asic.mdwn @@ -22,7 +22,11 @@ or ASIC for oneself. # Deliverables -See top-level bugreport [#589](https://bugs.libre-soc.org/show_bug.cgi?id=589#c0) +See top-level bugreport [#589](https://bugs.libre-soc.org/show_bug.cgi?id=589#c0) - all Milestones were achieved 100% successfully +as defined, including one additional Milestone added after the initial +approval in 2021, for +[power-modulo](https://bugs.libre-soc.org/show_bug.cgi?id=1044) +arithmetic (the basis of RSA, DH etc). **1) A set of general-purpose scalar instructions suitable for cryptographic applications as well as many other purposes** @@ -35,7 +39,8 @@ on big integer arithmetic on top of SVP64 vectorization. **2) Implementation and validation of the above instructions on the ISA simulator** -The implementation is scattered within the simulator code, which is available at: +As with all large software projects the implementation is scattered within +the simulator code, which is available at: Unit tests are available at: @@ -72,15 +77,18 @@ and directly run the test scripts referenced above. and element width overrides** These, when implemented also in HDL, will allow hyper-efficient acceleration of -many fundamental crypto algorithms. +many fundamental crypto algorithms in hardware. * [REMAP documentation](https://libre-soc.org/openpower/sv/remap/) * [Element width overrides documentation](https://libre-soc.org/openpower/sv/overview/#elwidths) -Implemented 100% in ISA simulator, allowing 100% successful implementation of Simple-V-PowerISA assembler to be made. +These are implemented 100% in the ISA simulator, allowing 100% successful implementation and simulation of Simple-V-PowerISA assembler to be made. +Once the HDL for these key criticl parts of SV are available (when +funded) then as usual the exact same assembler run under the +simulator may be run on FPGA or ASIC. (But limited budget of 2021-02-051 was insufficient to complete HDL -implementation.) +implementation) **5) Documentation and demonstration of the general-purpose instructions that happen to also help accelerate cryptographic algorithms** @@ -98,12 +106,15 @@ One catastrophic mistake made by many cryptographic instruction implementations is to create over-specific instructions. "multiply by 2 then subtract 5" for example (the basis of a RISC-V chacha20 "accelerator"!) Using our instructions, [our implementation of chacha20](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=crypto/chacha20/src/xchacha_encrypt_bytes_svp64.s;h=c1e0a8675cf679036b27de0bf83f8320ee36339a;hb=HEAD) -only has TEN INSTRUCTIONS in the inner loop entire algorithm. See: +only has TEN INSTRUCTIONS in the inner loop entire algorithm - a 50 to 100-fold +reduction in code density. See: [chacha20 design document](/openpower/sv/cookbook/chacha20). To run the chacha20 test in the ISA simulator, go to the `~/src/openpower-isa/crypto/chacha20` directory, run `make` and `SILENCELOG=1 ./test-chacha20` (warning: long running). +This unit test may also be run directly + Further reading: -- 2.30.2