From 04c401dda2eb751b1dfe1d614230e2d1790c581b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 17 Apr 2022 17:44:39 +0100 Subject: [PATCH] whitespace --- openpower/sv/bitmanip/appendix.mdwn | 43 ++++++++++++++++------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/openpower/sv/bitmanip/appendix.mdwn b/openpower/sv/bitmanip/appendix.mdwn index edf85fea0..e79894947 100644 --- a/openpower/sv/bitmanip/appendix.mdwn +++ b/openpower/sv/bitmanip/appendix.mdwn @@ -42,28 +42,33 @@ The key loop may be implemented with a 4-in, 2-out mul-twin-add ``` On Sat, Apr 16, 2022, 22:06 Jacob Lifshay wrote: and a mrsubcarry (the one actually needed by bigint division): -# for big_c - big_a * word_b -result <- RC + ~(RA * RB) + CARRY # this expression is wrong, needs further thought -CARRY <- HIGH_HALF(result) -RT <- LOW_HALF(result) - -turns out, after some checking with 4-bit words, afaict the correct algorithm for mrsubcarry is: -# for big_c - big_a * word_b -result <- RC + ~(RA * RB) + CARRY -result_high <- HIGH_HALF(result) -if CARRY <= 1 then # unsigned comparison - result_high <- result_high + 1 -end -CARRY <- result_high -RT <- LOW_HALF(result) + + # for big_c - big_a * word_b + result <- RC + ~(RA * RB) + CARRY # wrong, needs further thought + CARRY <- HIGH_HALF(result) + RT <- LOW_HALF(result) + +turns out, after some checking with 4-bit words, afaict the correct +algorithm for mrsubcarry is: + + # for big_c - big_a * word_b + result <- RC + ~(RA * RB) + CARRY + result_high <- HIGH_HALF(result) + if CARRY <= 1 then # unsigned comparison + result_high <- result_high + 1 + end + CARRY <- result_high + RT <- LOW_HALF(result) afaict, that'll make the following algorithm work: -so the inner loop in the bigint division algorithm would end up being (assuming n, d, and q all fit in registers): -li r3, 1 # carry in for subtraction -mtspr CARRY, r3 # init carry spr -setvl loop_count -sv.mrsubcarry rn.v, rd.v, rq.s, rn.v +so the inner loop in the bigint division algorithm would end up being +(assuming n, d, and q all fit in registers): + + li r3, 1 # carry in for subtraction + mtspr CARRY, r3 # init carry spr + setvl loop_count + sv.mrsubcarry rn.v, rd.v, rq.s, rn.v ``` This algorithm may be morphed into a pair of Vector operations by temporary -- 2.30.2