From 04efa224a8290bb7e25864f84c487f7afa28fa22 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 25 Sep 2023 17:57:19 +0100 Subject: [PATCH] whitespace additions on lbzu to make more like PDF, also added brackets around regs --- openpower/isa/fixedload.mdwn | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index 93297dcc..20252b28 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -76,10 +76,14 @@ Pseudo-code: RT <- ([0] * (XLEN-8)) || MEM(EA, 1) RA <- EA -Description:Let the effective address (EA) be the sum (RA)+ D. The -byte in storage addressed by EA is loaded into RT 56:63. -RT0:55 are set to 0. +Description: + +Let the effective address (EA) be the sum (RA)+ D. The +byte in storage addressed by EA is loaded into RT[56:63]. +RT[0:55] are set to 0. + EA is placed into register RA. + If RA=0 or RA=RT, the instruction form is invalid. Special Registers Altered: -- 2.30.2