From 051b8e6688cf6d78ea283de1a20bdf1983ab17e4 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Tue, 20 Sep 2022 01:09:45 +0300 Subject: [PATCH] power_insn: support common branch disassembly --- src/openpower/decoder/power_insn.py | 14 ++++++++++++++ src/openpower/sv/trans/test_pysvp64dis.py | 9 +++++++++ 2 files changed, 23 insertions(+) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 5fc8f00c..073d4d77 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1733,6 +1733,20 @@ class BranchBaseRM(SZBaseRM, BaseRM): CTR: BaseRM[19] VLS: BaseRM[20] + def specifiers(self, record): + if self.ALL: + yield "all" + if self.SNZ: + yield "snz" + if self.SL: + yield "sl" + if self.SLu: + yield "slu" + if self.LRu: + yield "lru" + + yield from super().specifiers(record=record) + class BranchSimpleRM(BranchBaseRM): """branch: simple mode""" diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index f3f014f8..53d854ca 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -255,6 +255,15 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) + def test_16_bc(self): + expected = [ + "sv.bc/all 12,*1,0xc", + "sv.bc/snz 12,*1,0xc", + "sv.bc/all/sl/slu 12,*1,0xc", + "sv.bc/all/snz/sl/slu/lru 12,*1,0xc", + ] + self._do_tst(expected) + if __name__ == "__main__": unittest.main() -- 2.30.2