From 05233f0647d0959065eb0c8297da1c9fb41d84c0 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 11 Aug 2020 13:33:51 +0100
Subject: [PATCH]

---
 3d_gpu/architecture/regfile.mdwn | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 0988b42e2..483ea4b49 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -4,13 +4,14 @@ Discussion:
 
 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008368.html>
 
-A minimum of 4 register files are required for POWER:
+These register files are required for POWER:
 
 * Floating-point
 * Integer
 * Control and Condition Code Registers (CR0-7)
 * SPRs (Special Purpose Registers)
-* Fast Registers (PC, MSR, CTR, LR, SRR0, SRR1 etc.)
+* Fast Registers (CTR, LR, SRR0, SRR1 etc.)
+* "State" Registers (CIA, MSR, SimpleV VL)
 
 Source code:
 
@@ -28,14 +29,16 @@ For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
   - CA(32) - 2-bit
   - OV(32) - 2-bit
   - SO     - 1 bit
-* FAST regfile: 7x 64-bit, full 3R2W (possibly greater)
-  - MSR: 64-bit
-  - PC: 64-bit
+* FAST regfile: 5x 64-bit, full 3R2W (possibly greater)
   - LR: 64-bit
   - CTR: 64-bit
   - TAR: 64-bit
   - SRR1: 64-bit
   - SRR2: 64-bit
+* STATE regfile: 3x 64-bit, 2R1W (possibly greater)
+  - MSR: 64-bit
+  - PC: 64-bit
+  - SVSTATE: 64-bit
 
 # Connectivity between regfiles and Function Units
 
-- 
2.30.2