From 053bb85b3220986f56fbbd24bd5bc7c04dea4ce6 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 20 Oct 2017 14:18:00 +0100 Subject: [PATCH] arch-arm: Removing FlushPipe fault, using SquashAfter This Patch is removing the FlushPipe ArmFault, which was used for flushing the pipeline in favour of the general IsSquashAfter StaticInstr flag. Using a fault was preventing tracers from tracing barriers like ISB and from adding them to the instruction count Change-Id: I176e9254eca904694f2f611eb486c55e50ec61ff Signed-off-by: Giacomo Travaglini Reviewed-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/5361 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/faults.cc | 21 +-------------------- src/arch/arm/faults.hh | 10 ---------- src/arch/arm/insts/pseudo.cc | 12 ++++++------ src/arch/arm/isa/insts/misc.isa | 7 +++---- src/arch/arm/isa/insts/misc64.isa | 11 +++++------ 5 files changed, 15 insertions(+), 46 deletions(-) diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 740d71d02..ef9d05a13 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2014, 2016 ARM Limited + * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -278,11 +278,6 @@ template<> ArmFault::FaultVals ArmFaultVals::vals = { "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat() }; -template<> ArmFault::FaultVals ArmFaultVals::vals = { - // Some dummy values - "Pipe Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, - 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() -}; template<> ArmFault::FaultVals ArmFaultVals::vals = { // Some dummy values "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, @@ -1398,19 +1393,6 @@ SystemError::routeToHyp(ThreadContext *tc) const return toHyp; } -void -FlushPipe::invoke(ThreadContext *tc, const StaticInstPtr &inst) { - DPRINTF(Faults, "Invoking FlushPipe Fault\n"); - - // Set the PC to the next instruction of the faulting instruction. - // Net effect is simply squashing all instructions behind and - // start refetching from the next instruction. - PCState pc = tc->pcState(); - assert(inst); - inst->advancePC(pc); - tc->pcState(pc); -} - void ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { DPRINTF(Faults, "Invoking ArmSev Fault\n"); @@ -1443,7 +1425,6 @@ template class ArmFaultVals; template class ArmFaultVals; template class ArmFaultVals; template class ArmFaultVals; -template class ArmFaultVals; template class ArmFaultVals; template class AbortFault; template class AbortFault; diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 8d72dee91..de5061bed 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -545,15 +545,6 @@ class SystemError : public ArmFaultVals bool routeToHyp(ThreadContext *tc) const override; }; -// A fault that flushes the pipe, excluding the faulting instructions -class FlushPipe : public ArmFaultVals -{ - public: - FlushPipe() {} - void invoke(ThreadContext *tc, const StaticInstPtr &inst = - StaticInst::nullStaticInstPtr) override; -}; - // A fault that flushes the pipe, excluding the faulting instructions class ArmSev : public ArmFaultVals { @@ -592,7 +583,6 @@ template<> ArmFault::FaultVals ArmFaultVals::vals; template<> ArmFault::FaultVals ArmFaultVals::vals; template<> ArmFault::FaultVals ArmFaultVals::vals; template<> ArmFault::FaultVals ArmFaultVals::vals; -template<> ArmFault::FaultVals ArmFaultVals::vals; template<> ArmFault::FaultVals ArmFaultVals::vals; diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc index ab38e29ea..aa3d93d6e 100644 --- a/src/arch/arm/insts/pseudo.cc +++ b/src/arch/arm/insts/pseudo.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014,2016 ARM Limited + * Copyright (c) 2014,2016-2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -190,6 +190,9 @@ McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, flags[IsNonSpeculative] = true; iss = _iss; miscReg = _miscReg; + + if (miscReg == MISCREG_DCCMVAC) + flags[IsSquashAfter] = true; } Fault @@ -207,12 +210,9 @@ McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const if (hypTrap) { return std::make_shared(machInst, iss, EC_TRAPPED_CP15_MCR_MRC); - } - - if (miscReg == MISCREG_DCCMVAC) - return std::make_shared(); - else + } else { return NoFault; + } } std::string diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 4681d50a9..b42c9f9dd 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -1070,12 +1070,11 @@ let {{ return std::make_shared(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); } - fault = std::make_shared(); ''' isbIop = InstObjParams("isb", "Isb", "ImmOp", {"code": isbCode, "predicate_test": predicateTest}, - ['IsSerializeAfter']) + ['IsSerializeAfter', 'IsSquashAfter']) header_output += ImmOpDeclare.subst(isbIop) decoder_output += ImmOpConstructor.subst(isbIop) exec_output += PredOpExecute.subst(isbIop) @@ -1087,12 +1086,12 @@ let {{ return std::make_shared(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); } - fault = std::make_shared(); ''' dsbIop = InstObjParams("dsb", "Dsb", "ImmOp", {"code": dsbCode, "predicate_test": predicateTest}, - ['IsMemBarrier', 'IsSerializeAfter']) + ['IsMemBarrier', 'IsSerializeAfter', + 'IsSquashAfter']) header_output += ImmOpDeclare.subst(dsbIop) decoder_output += ImmOpConstructor.subst(dsbIop) exec_output += PredOpExecute.subst(dsbIop) diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index 08902abe8..ac9f0a960 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -139,16 +139,15 @@ let {{ decoder_output += BasicConstructor64.subst(unknown64Iop) exec_output += BasicExecute.subst(unknown64Iop) - isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", - "fault = std::make_shared();", - ['IsSerializeAfter']) + isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "", + ['IsSerializeAfter', 'IsSquashAfter']) header_output += BasicDeclare.subst(isbIop) decoder_output += BasicConstructor64.subst(isbIop) exec_output += BasicExecute.subst(isbIop) - dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", - "fault = std::make_shared();", - ['IsMemBarrier', 'IsSerializeAfter']) + dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "", + ['IsMemBarrier', 'IsSerializeAfter', + 'IsSquashAfter']) header_output += BasicDeclare.subst(dsbIop) decoder_output += BasicConstructor64.subst(dsbIop) exec_output += BasicExecute.subst(dsbIop) -- 2.30.2