From 053db23629d83f48bd2bf8bff6bd156257cf429f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 31 Mar 2022 15:54:22 +0100 Subject: [PATCH] set Tercel to default into Quad SPI mode --- tercel/wishbone_spi_master.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tercel/wishbone_spi_master.v b/tercel/wishbone_spi_master.v index 4cf64fa..c4aa904 100644 --- a/tercel/wishbone_spi_master.v +++ b/tercel/wishbone_spi_master.v @@ -65,8 +65,10 @@ module tercel_core( wire [31:0] device_version; // PHY configuration register 1 - // Defaults to standard SPI mode, 3BA, non-extended read/write (qspi_[read|write]_quad_io_en = 0), cs_extra_idle_cycles = 0, dummy cycle cont = 10, clock divisor 16 - reg [31:0] phy_cfg1 = 32'h00000a10; + // Defaults to Quad SPI mode, 3BA, + // non-extended read/write (qspi_[read|write]_quad_io_en = 0), + // cs_extra_idle_cycles = 0, dummy cycle cont = 10, clock divisor 16 + reg [31:0] phy_cfg1 = 32'h00020a10; // Defaults to compatibility with Micron N25Q/512MB and similar 3BA/4BA capable devices, with multicycle and write disabled // Note that the N25Q does not support normal reads in QSPI mode, so we leave the QSPI normal read commands equal -- 2.30.2