From 0543987900782be84ae2d18e63bffffa2a5b0457 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 7 Apr 2022 00:04:55 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 4b56ef590..82ca2ea2c 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -693,3 +693,39 @@ end:
 # TODO LRu example
 
 show why LRu would be useful in a loop.
+
+v3.0 pseudocode for `bclrl`:
+
+```
+if (mode_is_64bit) then M <- 0
+else M <- 32
+if ¬BO[2]  then CTR <- CTR - 1
+ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
+cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
+if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
+if LK then LR <-iea CIA + 4
+```
+
+the latter part for SVP64 `bclrl` becomes:
+
+```
+for i in 0 to VL-1:
+    ...
+    ...
+    cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
+    if ctr_ok & cond_ok then
+       NIA <-iea LR[0:61] || 0b00
+       lr_ok = 1
+    if LK & lr_ok then LR <-iea CIA + 4
+```
+
+The reason why should be clear from this being a Vector loop:
+unconditional destruction of LR when LK=1 makes `bclrl`
+ineffective.  However if the change to LR only occurs if
+the branch is taken then it becomes a useful instruction.
+
+The following pseudocode should **not** be implemented because
+it violates the fundamental principle of SVP64 which is that
+SVP64 looping is a thin wrapper around Scalar Instructions.
+The pseducode below is more an actual Vector ISA Branch and
+as such is not aporopriate:
-- 
2.30.2