From 057b1428bcb8bfe8669650f3823c08f1ae7ab010 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 20 Feb 2022 23:58:58 +0000 Subject: [PATCH] add syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again --- src/soc/experiment/dcache.py | 4 ++-- src/soc/experiment/icache.py | 2 +- src/soc/regfile/regfile.py | 7 +++++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index ce1967bd..9e75cc01 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -747,10 +747,10 @@ class DCache(Elaboratable, DCacheConfig): if self.microwatt_compat: # reduce way sizes and num lines - super().__init__(NUM_LINES = 8, + super().__init__(NUM_LINES = 4, NUM_WAYS = 1, TLB_NUM_WAYS = 1, - TLB_SET_SIZE=16) # XXX needs device-tree entry + TLB_SET_SIZE=4) # XXX needs device-tree entry else: super().__init__() diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 8e457be5..6ed9ed44 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -339,7 +339,7 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig): # reduce way sizes and num lines ICacheConfig.__init__(self, NUM_LINES = 4, NUM_WAYS = 1, - TLB_SIZE=16 # needs device-tree update + TLB_SIZE=4 # needs device-tree update ) else: ICacheConfig.__init__(self) diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py index 07cee2dd..2427a680 100644 --- a/src/soc/regfile/regfile.py +++ b/src/soc/regfile/regfile.py @@ -56,7 +56,8 @@ class Register(Elaboratable): def elaborate(self, platform): m = Module() - self.reg = reg = Signal(self.width, name="reg", reset=self.reset) + self.reg = reg = Signal(self.width, name="reg", reset=self.reset, + attrs={'syn_ramstyle': "block_ram"}) if self.synced: domain = m.d.sync @@ -290,7 +291,9 @@ class RegFile(Elaboratable): def elaborate(self, platform): m = Module() bsz = int(log(self.width) / log(2)) - regs = Array(Signal(self.width, name="reg") for _ in range(self.depth)) + regs = Array(Signal(self.width, name="reg", + attrs={'syn_ramstyle': "block_ram"}) \ + for _ in range(self.depth)) # read ports. has write-through detection (returns data written) for rp in self._rdports: -- 2.30.2