From 0592c5ba0a7daad0328d7b524bf3e881ab9f84dd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Feb 2021 13:21:31 +0000 Subject: [PATCH] add comments, missing that VL loop ends after execution if no_out_vec set SVP64 TestIssuer --- src/soc/simple/issuer.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index b15298cb..f77788ec 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -304,7 +304,8 @@ class TestIssuerInternal(Elaboratable): sync += core.raw_insn_i.eq(dec_opcode_i) sync += core.bigendian_i.eq(self.core_bigendian_i) # TODO: loop into INSN_FETCH if it's a vector instruction - # and VL == 0 + # and VL == 0. this because VL==0 is a for-loop + # from 0 to 0 i.e. always, always a NOP. m.next = "INSN_EXECUTE" # move to "execute" with m.State("INSN_EXECUTE"): @@ -317,7 +318,8 @@ class TestIssuerInternal(Elaboratable): with m.If(exec_pc_valid_o): # TODO: update SRCSTEP here # TODO: loop into INSN_EXECUTE if it's a vector instruction - # and SRCSTEP != VL-1 + # and SRCSTEP != VL-1 and PowerDecoder.no_out_vec + # is True # unless PC / SVSTATE was modified, in that case do # go back to INSN_FETCH. m.next = "INSN_FETCH" -- 2.30.2