From 059639bb49c6984b8aa138df62157cc27a84b898 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 21 Feb 2022 18:41:52 +0000
Subject: [PATCH] add debug print statements to investigate FakePHY add some
 more names on dfi.Interface instances, again to see what is going on in
 gtkwave traces of SocTest nmigen simulation

---
 gram/core/controller.py | 3 ++-
 gram/dfii.py            | 4 ++++
 gram/phy/dfi.py         | 3 +++
 gram/phy/fakephy.py     | 7 ++++---
 4 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/gram/core/controller.py b/gram/core/controller.py
index 15aaaf7..9693893 100644
--- a/gram/core/controller.py
+++ b/gram/core/controller.py
@@ -64,7 +64,8 @@ class gramController(Elaboratable):
             bankbits=geom_settings.bankbits,
             nranks=phy_settings.nranks,
             databits=phy_settings.dfi_databits,
-            nphases=phy_settings.nphases)
+            nphases=phy_settings.nphases,
+            name="mem_dfi")
 
         self._clk_freq = clk_freq
 
diff --git a/gram/dfii.py b/gram/dfii.py
index 895e654..323ba97 100644
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -59,6 +59,7 @@ class PhaseInjector(Elaboratable):
 
 class DFIInjector(Elaboratable):
     def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
+        print ("nranks", nranks, "nphases", nphases)
         self._nranks = nranks
 
         self._inti = dfi.Interface(addressbits, bankbits,
@@ -84,6 +85,9 @@ class DFIInjector(Elaboratable):
         for n, phase in enumerate(self._phases):
             m.submodules['phase_%d' % n] = phase
 
+        for phase in self._inti.phases:
+            print ("phase", phase)
+
         with m.If(self._control.w_data[0]):
             m.d.comb += self.slave.connect(self.master)
         with m.Else():
diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py
index c2bdbbf..a436fee 100644
--- a/gram/phy/dfi.py
+++ b/gram/phy/dfi.py
@@ -34,6 +34,9 @@ def phase_description(addressbits, bankbits, nranks, databits):
 class Interface:
     def __init__(self, addressbits, bankbits, nranks, databits, nphases=1,
                        name=None):
+        print ("DFI Interface", name, "addr", addressbits,
+                "bankbits", bankbits, "nranks", nranks, "data", databits,
+                "phases", nphases)
         self.phases = []
         for p in range(nphases):
             p = Record(phase_description(addressbits, bankbits,
diff --git a/gram/phy/fakephy.py b/gram/phy/fakephy.py
index d1c4885..3b134cd 100644
--- a/gram/phy/fakephy.py
+++ b/gram/phy/fakephy.py
@@ -22,8 +22,8 @@ SDRAM_VERBOSE_OFF = 0
 SDRAM_VERBOSE_STD = 1
 SDRAM_VERBOSE_DBG = 2
 
-def Display(*args):
-    return Signal().eq(0)
+#def Display(*args):
+#    return Signal().eq(0)
 
 def Assert(*args):
     return Signal().eq(0)
@@ -511,7 +511,8 @@ class FakePHY(Elaboratable):
             bankbits    = self.bankbits,
             nranks      = self.settings.nranks,
             databits    = self.settings.dfi_databits,
-            nphases     = self.settings.nphases
+            nphases     = self.settings.nphases,
+            name="phy"
         )
 
     def elaborate(self, platform):
-- 
2.30.2