From 0597a3ea238ee100607271fb25a2d09fbd128bf0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 13 Aug 2019 10:23:07 -0700 Subject: [PATCH] Rename to XilinxDspPass --- passes/pmgen/xilinx_dsp.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index cd88f9449..31c0d48c5 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -127,8 +127,8 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) pm.blacklist(cell); } -struct Ice40DspPass : public Pass { - Ice40DspPass() : Pass("xilinx_dsp", "Xilinx: pack DSP registers") { } +struct XilinxDspPass : public Pass { + XilinxDspPass() : Pass("xilinx_dsp", "Xilinx: pack DSP registers") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -156,6 +156,6 @@ struct Ice40DspPass : public Pass { for (auto module : design->selected_modules()) xilinx_dsp_pm(module, module->selected_cells()).run_xilinx_dsp(pack_xilinx_dsp); } -} Ice40DspPass; +} XilinxDspPass; PRIVATE_NAMESPACE_END -- 2.30.2