From 059d29249d74559e221db34a7e9ef2c6629265f0 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 6 Feb 2020 13:47:13 +0000 Subject: [PATCH] hdl.mem: document Memory. --- nmigen/hdl/mem.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index 230bfa6..fc6c011 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -9,6 +9,28 @@ __all__ = ["Memory", "ReadPort", "WritePort", "DummyPort"] class Memory: + """A word addressable storage. + + Parameters + ---------- + width : int + Access granularity. Each storage element of this memory is ``width`` bits in size. + depth : int + Word count. This memory contains ``depth`` storage elements. + init : list of int + Initial values. At power on, each storage element in this memory is initialized to + the corresponding element of ``init``, if any, or to zero otherwise. + Uninitialized memories are not currently supported. + name : str + Name hint for this memory. If ``None`` (default) the name is inferred from the variable + name this ``Signal`` is assigned to. + + Attributes + ---------- + width : int + depth : int + init : list of int + """ def __init__(self, *, width, depth, init=None, name=None, simulate=True): if not isinstance(width, int) or width < 0: raise TypeError("Memory width must be a non-negative integer, not {!r}" -- 2.30.2