From 05a8e981ad6d359c0d748fe9fdda5e1270d53d78 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Wed, 4 Mar 2020 13:56:30 -0600 Subject: [PATCH] intel/isl: Require ISL_AUX_USAGE_HIZ_CCS_WT for HZ+CCS WT mode We also delete the badly named isl_surf_supports_hiz_ccs_wt. The name is misleading because it doesn't return whether or not the surface supports HiZ+CCS in write-through mode (any single-sampled HiZ+CCS capable surface does) but rather a heuristic decision about whether or not we want to enable write-through mode based on the usage flags in the isl_surf. Reviewed-by: Nanley Chery Part-of: --- src/intel/isl/isl.c | 10 ---------- src/intel/isl/isl.h | 8 -------- src/intel/isl/isl_emit_depth_stencil.c | 2 -- src/intel/isl/isl_surface_state.c | 3 +++ 4 files changed, 3 insertions(+), 20 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index d47313daf8e..e8889259cc7 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -2717,16 +2717,6 @@ isl_surf_get_depth_format(const struct isl_device *dev, } } -bool -isl_surf_supports_hiz_ccs_wt(const struct gen_device_info *dev, - const struct isl_surf *surf, - enum isl_aux_usage aux_usage) -{ - return aux_usage == ISL_AUX_USAGE_HIZ_CCS && - surf->samples == 1 && - surf->usage & ISL_SURF_USAGE_TEXTURE_BIT; -} - bool isl_swizzle_supports_rendering(const struct gen_device_info *devinfo, struct isl_swizzle swizzle) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index fbf31b19d00..596ec75c4af 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -2287,14 +2287,6 @@ uint32_t isl_surf_get_depth_format(const struct isl_device *dev, const struct isl_surf *surf); -/** - * @brief determines if a surface supports writing through HIZ to the CCS. - */ -bool -isl_surf_supports_hiz_ccs_wt(const struct gen_device_info *dev, - const struct isl_surf *surf, - enum isl_aux_usage aux_usage); - /** * @brief performs a copy from linear to tiled surface * diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 1ca40f63e48..9615a34f718 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -213,8 +213,6 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1; #if GEN_GEN >= 12 hiz.HierarchicalDepthBufferWriteThruEnable = - isl_surf_supports_hiz_ccs_wt(dev->info, info->depth_surf, - info->hiz_usage) || info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT; /* The bspec docs for this bit are fairly unclear about exactly what is diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 4b8592513d4..63ee7b10d2f 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -582,6 +582,9 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, */ assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT)); + if (isl_surf_usage_is_depth(info->surf->usage)) + assert(isl_aux_usage_has_hiz(info->aux_usage)); + if (isl_aux_usage_has_hiz(info->aux_usage)) { /* For Gen8-10, there are some restrictions around sampling from HiZ. * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode -- 2.30.2