From 05bf9da9a9f4b9be556e28a8b0468009c639e1ae Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 30 Aug 2020 15:45:03 +0100
Subject: [PATCH] reversal of FXM mask for one-hot selection in OP_MTCR decode

---
 libreriscv                             |  2 +-
 src/soc/decoder/power_decoder2.py      |  3 ++-
 src/soc/fu/cr/test/test_pipe_caller.py | 14 ++++++++++++++
 src/soc/simple/test/test_issuer.py     |  2 +-
 4 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/libreriscv b/libreriscv
index 8976b9bf..2f9e4490 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 8976b9bf14aab4e7bff0eabfa1412744ed0fe832
+Subproject commit 2f9e449034fd6963965c76e727cc4e3cfa3df9c6
diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index b0142c15..1bdcd3ff 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -557,7 +557,8 @@ class DecodeCROut(Elaboratable):
         m = Module()
         comb = m.d.comb
         op = self.dec.op
-        m.submodules.ppick = ppick = PriorityPicker(8)
+        m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
+                                                       reverse_o=True)
 
         comb += self.cr_bitfield.ok.eq(0)
         comb += self.whole_reg.ok.eq(0)
diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index b615c93f..fe794f89 100644
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -110,6 +110,20 @@ class CRTestCase(TestAccumulatorBase):
         p.assembly = '\n'.join(dis)+'\n'
         self.add_case(p, initial_cr=cr)
 
+    def case_mtocrf_regression(self):
+        """microwatt 1.bin regression, same hack as above.
+           106b4:   21 d9 96 7d     .long 0x7d96d921   # mtocrf 12, 0b01101101
+        """
+        mask = 0b01101101
+        dis = [f"mtocrf 12, {mask}"]
+        lst = bytes([0x21, 0xd9, 0x96, 0x7d]) # 0x7d96d921
+        cr = 0x529e08fe
+        initial_regs = [0] * 32
+        initial_regs[12] = 0xffffffffffffffff
+        p = Program(lst, bigendian)
+        p.assembly = '\n'.join(dis)+'\n'
+        self.add_case(p, initial_regs=initial_regs, initial_cr=cr)
+
     def case_mfocrf_1(self):
         lst = [f"mfocrf 2, 1"]
         cr = 0x1234
diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index f81eef12..91e68a71 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -281,7 +281,7 @@ class TestRunner(FHDLTestCase):
                 cr = yield from get_dmi(dmi, DBGCore.CR)
                 print ("after test %s cr value %x" % (test.name, cr))
 
-                # get CR
+                # get XER
                 xer = yield from get_dmi(dmi, DBGCore.XER)
                 print ("after test %s XER value %x" % (test.name, xer))
 
-- 
2.30.2