From 05d004d98d626cc3f0a73c694a0bf225787034f8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 13 Jun 2018 15:10:29 +0100 Subject: [PATCH] cross-reference issues under consideration --- simple_v_extension/simple_v_chennai_2018.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 82d9b1d36..5e8b8ff31 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -715,7 +715,7 @@ loop: \item 8/16-bit ops is it worthwhile adding a "start offset"? \\ (a bit like misaligned addressing... for registers)\\ or just use predication to skip start? - \item http://libre-riscv.org/simple\_v\_extension/\#issues + \item see http://libre-riscv.org/simple\_v\_extension/\#issues \end{itemize} } -- 2.30.2