From 05df3dbee434dc206c02314d4ff7d2a6faee1c4b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 28 May 2017 11:59:05 +0200 Subject: [PATCH] Add "setundef -anyseq" --- kernel/rtlil.h | 24 +++++++++++----------- passes/cmds/setundef.cc | 44 +++++++++++++++++++++++++++++++++++++++-- passes/sat/freduce.cc | 3 ++- 3 files changed, 56 insertions(+), 15 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9fee61aad..51a3fad6f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -911,7 +911,7 @@ public: std::vector ports; void fixup_ports(); - template void rewrite_sigspecs(T functor); + template void rewrite_sigspecs(T &functor); void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; @@ -1201,7 +1201,7 @@ public: module->design->module(type)->get_bool_attribute("\\keep")); } - template void rewrite_sigspecs(T functor); + template void rewrite_sigspecs(T &functor); }; struct RTLIL::CaseRule @@ -1213,7 +1213,7 @@ struct RTLIL::CaseRule ~CaseRule(); void optimize(); - template void rewrite_sigspecs(T functor); + template void rewrite_sigspecs(T &functor); RTLIL::CaseRule *clone() const; }; @@ -1224,7 +1224,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject ~SwitchRule(); - template void rewrite_sigspecs(T functor); + template void rewrite_sigspecs(T &functor); RTLIL::SwitchRule *clone() const; }; @@ -1234,7 +1234,7 @@ struct RTLIL::SyncRule RTLIL::SigSpec signal; std::vector actions; - template void rewrite_sigspecs(T functor); + template void rewrite_sigspecs(T &functor); RTLIL::SyncRule *clone() const; }; @@ -1246,7 +1246,7 @@ struct RTLIL::Process : public RTLIL::AttrObject ~Process(); - template void rewrite_sigspecs(T functor); + template void rewrite_sigspecs(T &functor); RTLIL::Process *clone() const; }; @@ -1295,7 +1295,7 @@ inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { } template -void RTLIL::Module::rewrite_sigspecs(T functor) +void RTLIL::Module::rewrite_sigspecs(T &functor) { for (auto &it : cells_) it.second->rewrite_sigspecs(functor); @@ -1308,13 +1308,13 @@ void RTLIL::Module::rewrite_sigspecs(T functor) } template -void RTLIL::Cell::rewrite_sigspecs(T functor) { +void RTLIL::Cell::rewrite_sigspecs(T &functor) { for (auto &it : connections_) functor(it.second); } template -void RTLIL::CaseRule::rewrite_sigspecs(T functor) { +void RTLIL::CaseRule::rewrite_sigspecs(T &functor) { for (auto &it : compare) functor(it); for (auto &it : actions) { @@ -1326,7 +1326,7 @@ void RTLIL::CaseRule::rewrite_sigspecs(T functor) { } template -void RTLIL::SwitchRule::rewrite_sigspecs(T functor) +void RTLIL::SwitchRule::rewrite_sigspecs(T &functor) { functor(signal); for (auto it : cases) @@ -1334,7 +1334,7 @@ void RTLIL::SwitchRule::rewrite_sigspecs(T functor) } template -void RTLIL::SyncRule::rewrite_sigspecs(T functor) +void RTLIL::SyncRule::rewrite_sigspecs(T &functor) { functor(signal); for (auto &it : actions) { @@ -1344,7 +1344,7 @@ void RTLIL::SyncRule::rewrite_sigspecs(T functor) } template -void RTLIL::Process::rewrite_sigspecs(T functor) +void RTLIL::Process::rewrite_sigspecs(T &functor) { root_case.rewrite_sigspecs(functor); for (auto it : syncs) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 03a5a123f..9827ac0b1 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -30,6 +30,7 @@ struct SetundefWorker { int next_bit_mode; uint32_t next_bit_state; + vector siglist; RTLIL::State next_bit() { @@ -50,6 +51,11 @@ struct SetundefWorker void operator()(RTLIL::SigSpec &sig) { + if (next_bit_mode == 2) { + siglist.push_back(&sig); + return; + } + for (auto &bit : sig) if (bit.wire == NULL && bit.data > RTLIL::State::S1) bit = next_bit(); @@ -75,6 +81,9 @@ struct SetundefPass : public Pass { log(" -one\n"); log(" replace with bits set (1)\n"); log("\n"); + log(" -anyseq\n"); + log(" replace with $anyseq drivers (for formal)\n"); + log("\n"); log(" -random \n"); log(" replace with random bits using the specified integer als seed\n"); log(" value for the random number generator.\n"); @@ -109,13 +118,18 @@ struct SetundefPass : public Pass { worker.next_bit_mode = 1; continue; } + if (args[argidx] == "-anyseq") { + got_value = true; + worker.next_bit_mode = 2; + continue; + } if (args[argidx] == "-init") { init_mode = true; continue; } if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; - worker.next_bit_mode = 2; + worker.next_bit_mode = 3; worker.next_bit_state = atoi(args[++argidx].c_str()) + 1; for (int i = 0; i < 10; i++) worker.next_bit(); @@ -126,7 +140,7 @@ struct SetundefPass : public Pass { extra_args(args, argidx, design); if (!got_value) - log_cmd_error("One of the options -zero, -one, or -random must be specified.\n"); + log_cmd_error("One of the options -zero, -one, -anyseq, or -random must be specified.\n"); for (auto module : design->selected_modules()) { @@ -241,6 +255,32 @@ struct SetundefPass : public Pass { } module->rewrite_sigspecs(worker); + + if (worker.next_bit_mode == 2) + { + vector siglist; + siglist.swap(worker.siglist); + + for (auto sigptr : siglist) + { + SigSpec &sig = *sigptr; + int cursor = 0; + + while (cursor < GetSize(sig)) + { + int width = 0; + while (cursor+width < GetSize(sig) && sig[cursor+width] == State::Sx) + width++; + + if (width > 0) { + sig.replace(cursor, module->Anyseq(NEW_ID, width)); + cursor += width; + } else { + cursor++; + } + } + } + } } } } SetundefPass; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 77263f6a2..a3028bfce 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -687,7 +687,8 @@ struct FreduceWorker } std::map bitusage; - module->rewrite_sigspecs(CountBitUsage(sigmap, bitusage)); + CountBitUsage bitusage_worker(sigmap, bitusage); + module->rewrite_sigspecs(bitusage_worker); if (!dump_prefix.empty()) dump(); -- 2.30.2