From 061e890c97c41d95b382d730c01ed7054d3dd3c1 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 14 Dec 2018 16:46:16 +0000 Subject: [PATCH] back.pysim: make initial phase configurable. --- nmigen/back/pysim.py | 6 ++++-- nmigen/compat/sim/__init__.py | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index f0bfba1..d09c981 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -250,15 +250,17 @@ class Simulator: pass self.add_process(sync_process()) - def add_clock(self, period, domain="sync"): + def add_clock(self, period, phase=None, domain="sync"): if self._fastest_clock == self._epsilon or period < self._fastest_clock: self._fastest_clock = period half_period = period / 2 + if phase is None: + phase = half_period clk = self._domains[domain].clk def clk_process(): yield Passive() - yield Delay(half_period) + yield Delay(phase) while True: yield clk.eq(1) yield Delay(half_period) diff --git a/nmigen/compat/sim/__init__.py b/nmigen/compat/sim/__init__.py index 4ee0454..8219cf9 100644 --- a/nmigen/compat/sim/__init__.py +++ b/nmigen/compat/sim/__init__.py @@ -18,7 +18,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim: for domain, period in clocks.items(): - sim.add_clock(period / 1e9, domain) + sim.add_clock(period / 1e9, domain=domain) for domain, process in generators.items(): - sim.add_sync_process(process, domain) + sim.add_sync_process(process, domain=domain) sim.run() -- 2.30.2