From 062203ae18fc7a25114fb5746f636a0439cc6cec Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 2 Mar 2017 21:22:41 -0800 Subject: [PATCH] xilinx pcie: add the high PCIe address bits (physical path) The format is taken from here: http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/pci/xilinx-pcie.txt --- .../ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala index 2e826db..b4fad21 100644 --- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala @@ -182,7 +182,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), "ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _)) => - ResourceMapping(address, 0) }, + ResourceMapping(address, BigInt(0x02000000) << 64) }, "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( "interrupt-controller" -> Nil, "#address-cells" -> ofInt(0), -- 2.30.2