From 06321976a7dc0535bcfa42f7e3d7dbb53ec14977 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 4 Jun 2020 11:54:15 +0200 Subject: [PATCH] Add dram core as submodule --- examples/ecpix5.py | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/ecpix5.py b/examples/ecpix5.py index ddc8bf3..7bf866b 100644 --- a/examples/ecpix5.py +++ b/examples/ecpix5.py @@ -165,6 +165,7 @@ class DDR3SoC(CPUSoC, Elaboratable): m.submodules.timer = self.timer m.submodules.intc = self.intc m.submodules.ddrphy = self.ddrphy + m.submodules.dramcore = self.dramcore m.submodules.sysclk = SysClocker() -- 2.30.2