From 0655cc8f1ce274ac45c4f32793b6a6437c078825 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Sep 2018 02:28:41 +0100 Subject: [PATCH] sv: rd, rs1/2/3 become virtual so that sv_insn_t can override them --- riscv/decode.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/riscv/decode.h b/riscv/decode.h index f9e3b6f..7c2b89e 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -76,10 +76,10 @@ public: int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); } int64_t u_imm() { return int64_t(b) >> 12 << 12; } int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); } - uint64_t rd() { return x(7, 5); } - uint64_t rs1() { return x(15, 5); } - uint64_t rs2() { return x(20, 5); } - uint64_t rs3() { return x(27, 5); } + uint64_t virtual rd() { return x(7, 5); } + uint64_t virtual rs1() { return x(15, 5); } + uint64_t virtual rs2() { return x(20, 5); } + uint64_t virtual rs3() { return x(27, 5); } uint64_t rm() { return x(12, 3); } uint64_t csr() { return x(20, 12); } -- 2.30.2